Audio Library and 8k Sampling Frequency.

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Stanleyvc

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The SGTL5000 codex have the follow Sampling Frequency 's: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48, 96.

Can the Audio library also 8K Sampling Frequency handle?

Thanks.
 
Actually, the sampling rate is hard coded at 44.1kHz. In order to operate at lower or higher frequencies, you‘d have to tweak at least the I2S_output object to send with lower master clock, bit clock, and frame clock.
 
Thanks,

In the library, see this:
Code:
#elif F_CPU == 180000000  
  #define MCLK_MULT 16
  #define MCLK_DIV  255
  #define MCLK_SRC  0

Can you tel me what the formula is for the setting 's.

Thanks.
 
The KINETIS K20 reference manual (I2S section) can tell it more precisely than I can. Basically, you‘ll have to set the I2S master clock generator to 256 times the sample frequency by choosing the appropriate internal clock source first, and then by setting the multiplier and the divider to program the fractional clock divider unit. In the above example the system clock is selected as the source (SRC=0), which corresponds to F_CPU = 180MHz in this configuration. Now, these 180 MHz are multiplied by 16 and divided by 255 which gives a I2S master clock of 11.294 MHz, corresponding to a sample rate of 44117.7Hz which is within the allowed 4% tolerance band near the official 44.1kHz.
For 8 kHz, you‘d need a master clock of 256 x 8kHz = 2.048MHz.
Now it depends on your selected Teensy Model and clock speed to determine the multiplier and divider parameters. With the most common Teensy 3.2 and a 96MHz System clock, you could select as a first approach MULT=1 and DIV=47 to get a real master clock of 2.0426MHz corresponding to a sample rate of 7.979kHz which is only 0.27% apart.
 
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