Just have to say thanks! Thanks to PJRC & Paul for making Teensy product line!

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Godfear17

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Got my first Teensy, boom mind blown! A snassy 3.5 got two of them to play with.

I just love the fact it's a perfect in-between Arduino and RasberryPI/Beaglebone. Where I don't need the "full computer" os, all that, but just want the horsepower.

Good grief and it's overclockable. It's absolutely amazingly stunning work of art.

Just on the larger ram/memory alone, I'd be impressed but its list of features is just mind-blowing for the price. It's the right shape, size, you name it. Even if it was slightly wider would be fine with me.

Now I have to order some 3.6's, thanks. This just makes any project doable on a single microcontroller, no more hacking two or three 328p's together LOL!!!!

Most energetically, Thank you Paul for making this for us! Can't not wait to see what you will make next! I can tell I'm gonna be a long time buyer of these puppies!

Now I'm all like the apple fanboys do. OOOOh what will the 3.7 or 4.0 Teensy be like? Hmmm? lol I mean will we see 200? 250mhz Teensy? Multicore? Exciting times!

p.s.
Product suggestion?
IF/When you ever make a 3.5/3.6 with a nRF24L01P+PA+LNA rf onboard with a sma port for external antenna I wouldn't have to use anything extra lol!
 
defragster said:
Dual USB ? or some other 'issue'?
Click to expand...

The term dual issue tends to refer to the chip being able to issue two instructions at the same time (assuming they don't conflict with each other). In general, it is invisible to the user, but the compiler can schedule two independent instructions with the hopes that will be executed at the same time.
 
Thanks - I thought maybe the sphellhellper fixed "2 x USB".

IMXRT1050RM.pdf::
The processor has an in-order super-scalar pipeline by which many instructions can be dual-issued, including load/load and load/store instruction pairs because of multiple memory interfaces.
Click to expand...
 
TL;DR = dual issue means sometimes a CPU can execute 2 instructions per clock cycle.

https://stackoverflow.com/questions/8014739/what-exactly-is-a-dual-issue-processor

On top of the pipeline and 2 ALUs, it has 64 bit bus for instructions and dual interleaved 32 bit buses for data, to support sustained running 2 instructions per clock (if from the ITCM region) and to have the ability to actually perform 2 loads or 1 load and 1 store at the same time (if interleaved in the DTCM region), or from other memory that's been cached in the two 32K L1 caches.
 
PaulStoffregen said:
600 MHz, dual-issue.
Click to expand...

600MHzeees? When? Where? RF? How Much? When?

tenor.jpg tenor (1).jpg
8QmIp.jpg a4c.jpg mentira.jpg
 
"Most energetically, Thank you Paul for making this for us! "

How as a community can we help PJRC drive more sales? Maybe stuff like YouTube posts of projects, Tweets of our projects, posting q/a on the Arduino forum (trojan horse advertising), word of mouth?

I'm sure Paul will welcome any help.
 
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