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Thread: What if we could make a fully custom chip?

  1. #1
    Senior Member PaulStoffregen's Avatar
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    What if we could make a fully custom chip?

    I talked with a couple people from SiFive at Crowd Supply's Teardown 2018 Conference about someday (maybe, very hypothetically) using RISC-V for future Teensy.

    Just to be clear, Teensy 4.x will definitely be based on NXP's iMXRT chips, which use ARM Cortex-M7.

    But in the more distant future, RISC-V and especially the prospect of a fully custom chip seems quite intriguing. Whether PJRC could afford to fund such a thing alone is a good question. Well, today the answer is probably no. In the future, a few years from now, who knows? Maybe it could be done as a collaboration with other maker-focused companies like Adafruit or Sparkfun. Or maybe an ARM license isn't as unobtainable as it might seem, with Arduino now partially owned by ARM.

    I must say, even though I did make a chip 25 years ago as a grad student, this idea still seems a little crazy. Then again, maybe it's more achievable than I'm imagining?

    So the question... what would go into a custom chip? For anything analog, how would it be designed & verified?

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    would this chip be capable to what the VLSI is doing http://www.vlsi.fi/en/products/vs1010.html?

    BTW
    I only look for a good 32-bit complex DSP engine (no FP needed but large accumulator) with multi-channel TDM I/O, 4-bit SDIO, and fast memory access.

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    Senior Member+ MichaelMeissner's Avatar
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    Well obviously you would want a standard instruction set that is already supported by GCC, so that you don't have to worry about getting the support in. ARM, RISC-V, MIPS, etc. is fine, but if you start adding new 'features' it will balloon the costs. I seriously doubt that you would go that path, but you never know.

    While I've created 5 GCC targets for new processors back in the day. I tended to do just the compiler end and other people would work on binary utilities, debugger, libraries, simulator, in parallel, it is a lot of work to navigate the system, and you would need continuing support for it. It is even more work to navigate the political system if somebody new is starting the process. As I'm employed already to work on GCC, I wouldn't be available.

    But outside of the core ISA, there is a lot that can be done in terms of aux. functionality (i.e. adding analog support, various bus supports like CAN, serial, i2c, spi, etc.) that doesn't need a new compiler.

    I would hope that finally GDB support will be available.

    I suspect in terms of sales, it would probably need bluetooth/wifi to compete with the TenSilica boards.

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    RISC-V looks very interesting.

    What kind of footprint would something like that be? Breadboard compatible still possible?

  5. #5
    Senior Member PaulStoffregen's Avatar
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    Mundane as this sounds, near the top of my wish list is AVR timer emulation. Of course timers would probably want to have much more functionality, but it would be designed so everything is a superset of the AVR timers (eg, prescale up to 1024, not just 256 as we have now in NXP/Freescale Kinetis FTM/TPM timers) and the hardware would implement an extra set registers which exactly mimic the AVR timers.

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    Senior Member+ Theremingenieur's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    Mundane as this sounds, near the top of my wish list is AVR timer emulation. Of course timers would probably want to have much more functionality, but it would be designed so everything is a superset of the AVR timers (eg, prescale up to 1024, not just 256 as we have now in NXP/Freescale Kinetis FTM/TPM timers) and the hardware would implement an extra set registers which exactly mimic the AVR timers.
    Yes, and true 32bit capture and compare registers!!!

  7. #7
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by WMXZ View Post
    would this chip be capable to what the VLSI is doing http://www.vlsi.fi/en/products/vs1010.html?
    Pretty sure we already have that much capability, hardware-wise, on Teensy 3.x.

    On the software size, Frank's MP3 library runs well on 3.2 & higher. Of course we're missing some features like Ogg format. Small matter of programming....

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    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by Theremingenieur View Post
    true 32bit capture and compare registers!!!
    Yes, and with a FIFO feeding the DMA controller (or maybe even bus master DMA), so we can actually generate and analyze fast waveforms without bogging down the DMA controller and CPU.

    Even NXP's new iMXRT chip is all still 16 bit timers with 16 bit capture/compare, and only single buffered.

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    Senior Member+ Theremingenieur's Avatar
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    What I found working with the 32bit DSP instructions is that it’s extremely difficult to maintain the full 32bit resolution through complex calculations. Most times, a few bits at the end risk to become insignificant or you have to write your own routines for 64bit shifting and saturating. Thus I’d opt for 64bit DSP instructions so that you might always end up with 32 significant bits.

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    As a point of reference, a few years ago I backed a Kickstarter for "Navspark" which included a 100MHz 32bit LEON3 Sparc-V8 + IEEE-754 Compliant FPU, 1024KB Flash Memory + 212KB RAM, ~80uA/MHz @ 3.3V
    It is sort-of Arduino compatible. My understanding was the CPU per se was open source, although they added a proprietary block for their GPS processing engine. They are selling these for $25 so it's in the Teensy category in that respect. http://navspark.mybigcommerce.com/na...h-gps-glonass/

    (sorry, memory failure, it was "indiegogo" not kickstarter.)

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    Senior Member+ MichaelMeissner's Avatar
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    Quote Originally Posted by JBeale View Post
    As a point of reference, a few years ago I backed a Kickstarter for "Navspark" which included a 100MHz 32bit LEON3 Sparc-V8 + IEEE-754 Compliant FPU, 1024KB Flash Memory + 212KB RAM, ~80uA/MHz @ 3.3V
    It is sort-of Arduino compatible. My understanding was the CPU per se was open source, although they added a proprietary block for their GPS processing engine. They are selling these for $25 so it's in the Teensy category in that respect. http://navspark.mybigcommerce.com/na...h-gps-glonass/

    (sorry, memory failure, it was "indiegogo" not kickstarter.)
    It is Sparc core offered under dual license: https://www.gaisler.com/index.php/pr...ocessors/leon3

    Sparc was designed many years ago by Sun Microsystems https://en.wikipedia.org/wiki/SPARC.

    Note, Sparc has double precision in hardware, while the Teensy 3.5/3.6 only have single precision support. So I imagine for things like GPSes, the DP wins.

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    Senior Member+ Frank B's Avatar
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    I don't have any exprience with it, and i have no idea wether it is possible or not - but for me the idea of having some kind of programmable logic on the cpu would be interesting. One could create own "hardware" just by loading some code.
    Or, one can spin it further and place the "Teensy" on a fast FPGA ... with customizable periphery.....

    Edit: I just found this after 3 seconds google.. : https://github.com/SpinalHDL/VexRiscv

    Edit: Hehe, here is a SID.. http://www.fpgasid.de
    Last edited by Frank B; 09-17-2018 at 08:38 PM.

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    Senior Member pictographer's Avatar
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    The big selling point for RISC-V is that it's open source. If the PJRC variant were not entirely open, that would make it less interesting.

    The world would be a safer place if there were more computers and especially personal computers that could be inspected down to the gate level.

    Blocks I'd like:
    • Processor
    • Memory controller
    • Network controller
    • Display controller
    • Simple microcontrollers for IO
    • Power management

    Don't bother with analog because it's so much cheaper to add ICs per application than to try to compromise and combine analog and digital on one die.

    Maybe also features for security and safety:
    • Hardware RNG
    • Uninitialized memory to make a PUFF
    • Crypto-friendly instructions like barrel shifters among many other
    • Cryptographic operations like hash functions, etc.
    • Redundancy, EDAC

  14. #14
    Senior Member+ Frank B's Avatar
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    During the last days, I've seen some boards with a dual core RSIC V 64 Bit CPU (and features like a FFT, or a "audio accelarator" (whatever that is) in "hardware") on a FPGA.

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    I like the idea of having a cpu and an fpga in one package, and many of those are available. Maybe it's just a matter of picking the right line? That way we wouldn't need to think so much about which pins to break out.

    I'm sure antti from hackaday would be able to point at exactly the right product. Maybe even with analog peripherals already in.

  16. #16
    A hardware RNG (based on a noise diode) would be my first priority, and maybe a hardware AES-256 implementation. In addition, a hardware RSA-2048 implementation would be a real boon. Let's face it, many people make mistakes implenenting cryptographic systems, resulting in insecure IoT hardware, affecting millions.

    Also, the new Teensy would need to have support for Rust, a safe systems programming language. We need to dump C as it's eating the world.
    Last edited by bigpilot; 11-28-2018 at 12:12 PM.

  17. #17
    Senior Member pictographer's Avatar
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    Hardware random number generators are surprisingly difficult. The testing is necessarily statistical. Proving that your noise source isn't susceptible to bias from other activity in the chip and in the environment is also difficult.

  18. #18
    Using thermal noise from a diode shouldn't be too difficult and I don't believe an adversary would be able to manipulate it through external interference. I saw that the Teensy 3.2 uses dual ring oscillators to generate entropy and they specifically state that they cannot guarantee that it can't be manipulated. That has me somewhat worried. Why not use a noise diode, which is much simpler and nigh impossible to manipulate?

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    "well nigh impossible to manipulate"

    How sophisticated is the adversary? Can they manipulate voltage and temperature? Can they use standard failure analysis tool used by chip makers?

  20. #20
    I'm a great fan of RISC-V but I agree with previous posters that if the design isn't fully open-source there's little benefit. OTOH commercial companies may benefit from a closed design which enables vendor lock-in.

  21. #21
    Senior Member+ defragster's Avatar
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    SparkFun has SiFive Risc product for sale:

    HiFive1 - Arduino RISC-V Dev Board
    DEV-15148 RoHS
    $67.95
    Microcontroller: SiFive Freedom E310 (FE310)
    CPU: SiFive E31 CPU
    Architecture: 32-bit RV32IMAC
    Speed: 320+ MHz
    Performance: 1.61 DMIPs/MHz
    Memory: 16 KB Instruction Cache, 16 KB Data Scratchpad

  22. #22
    Senior Member PaulStoffregen's Avatar
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    Any idea what's different about the new version? I see a few more parts near the DC power jack. As nearly as I can see on Sparkfun's pages, all the info is exactly the same.

    Of course the solder mask color is different. I see a mention about black for the crowd funded version, green for production. But I have a HiFive1 which I purchased many months after their 1st Crowd Supply campaign. It has black solder mask.

  23. #23
    Senior Member+ defragster's Avatar
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    No - seems to be the same - I just saw it in the SparkFun 'Develop something new for 2019' email - for just a few extra dollars ... limit 1 per person. Other than larger EEPROM the T4 seems to outpace it glancing at the specs.

    The SiFive site you linked shows that same (f)E310 unit there and the only other is their hifive-unleashed unit for $999 on CrowdSource

  24. #24
    Senior Member PaulStoffregen's Avatar
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    Earlier this year at Crowd Supply's Teardown conference, I met 2 of the guys from SiFive. They mentioned a new version of the chip was coming. Maybe this new board is actually the new chip, but they're just copied and pasted all the old info for now?

    At Teardown, they were reluctant to give details about the upcoming chip refresh. They did say it'd have more than 16K memory, but wouldn't pin down how much more. Apparently the existing chip was meant to have I2C in hardware, but some sort of mistake was made in the design. They weren't really willing to directly admit that, but did sort-of suggest they had tried to make working I2C, but woudn't give any specific info or even say the new one would really have I2C hardware.

    The SiFive guys mostly talked about Linux. I don't want to speak too harshly of them, but I got an overall impression SiFive doesn't really understand microcontroller or really isn't serious about making a commercially competitive product.

  25. #25
    Senior Member+ defragster's Avatar
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    Following the unleased U540 link to crowdsource for $999 purchase shows it is way more than the $60 board - with a Linux base rather Arduino compatible like the E310.
    Freedom Unleashed 64-bit, Linux-capable system-on-chip (SoC) platform. Meet the HiFive Unleashed, the world’s first RISC-V-based, Linux-capable development board.
    That would seem to be the 'NEW' board ... They made and shipped the 198 initial backer's boards and planned a new November build ... accepting pre-orders ...

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