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Thread: Teensy 3.6 I2S Slave Mode Question

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    Teensy 3.6 I2S Slave Mode Question

    I reviewed the handling of 24 bit I2S microphones (which I use to capture ambient noise) and believe the automatic decimation to 16 bits as coded will work fine. I ran into another mental snag while doing system analysis.

    I also have an array microphone with I2S support. The issue is that it want's to be the I2S master as well as appearing as a 24 bit I2S source (like the above microphones).

    As a note, the only input/output devices I'm implementing will be the I2S slave in and out to the array mic. An I2S master in R/L for the 2 I2S microphones, A DAC audio out and a ADC audio in (eg a pseudo codec). AGC and VOX are implemented as intermediate audio dsp processes. That's it.

    I need to know if I have to do anything special to let that I2S channel with audio decimated to 16 bits AND let it be the sole framing master all of the rest of the audio I/O.

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    are we still talking about SPH0645LM4H?
    array of microphones? more than 2?

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    No. Different microphone. The SPH0645LM4H microphones are running under Teensy Audio on their own master I2S input channel with the 24 to 16 bit decimation discussed in that thread.

    This is a separate XMOS array mono microphone with 24 bit audio in and 24 bit audio out. The implementation of the I2S indicates that the array mic will supply BCLK and LRCLK (eg it wants to master its channel) so the Teensy 3.6 will need to run that I2S channel in slave mode.

    What I'm wondering if I need to do anything special to integrate that single slave channel with the rest of the Teensy Audio environment or am I missing something.

  4. #4
    Senior Member PaulStoffregen's Avatar
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    Generally I2S slave mode can't be combined with any other inputs or outputs, even ADC or DAC. Everything else is effectively master mode, sync'd to Teensy's clock. I2S slave mode uses the external clock and causes the audio library to run at that speed dictated by the external clock.

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    I fully understand at this point as well as the issues in sample rate conversions for non synchronous i/o. Additionally it appears that the Teensy 3.6 has only one full duplex I2S channel. Since I need more than that, I have been looking into a minimal port to the STM32F413Zx which has 3 half duplex I2S channels and 2 full duplex i2s channels each of which can be independently run in master or slave modes. For my application I can actually allow one channel to provide master clocking for all of the others as slaves.

  6. #6
    Senior Member PaulStoffregen's Avatar
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    Teensy 3.2, 3.5 and 3.6 have hardware for 2 stereo input and 2 stereo output channels. They do share a common clock.

    In theory, quad channel I2S slave mode should be possible. Same with TDM slave mode. But to date, nobody has suggested even 1 realistic use case for any of those, so they're not even on the wish list yet.

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    Humm... IF... I2S quad slave was a realistic possibility then I could run the array mic input/output in using that as the master clock (BCLK, MCLK, LRCLK). The secondary microphones and the earphone I2S channels would be synchronous to that same clock (with all I/O in 24 to 16 bit decimation modes). The question then becomes can the DAC and ADC channels still be run DMA synchronously as a pseudo codec for the radio tx/rx audio. If so then Teensy 3.6 can work (which would be great).

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    Senior Member PaulStoffregen's Avatar
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    The ADC and DAC use the PDB timer to set their sample rate. There isn't any direct hardware mechanism for the on-chip timers to track an external clock. You could try to build code to adjust the timer in real time, but that would be tricky to do well. The existing code in the audio library configures the PDB timer in the normal way, where PDB clocks from F_BUS and generates events when that timer hits the programmed threshold.

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    Senior Member+ Frank B's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    The ADC and DAC use the PDB timer to set their sample rate. There isn't any direct hardware mechanism for the on-chip timers to track an external clock.
    I'm working on this...
    The manual says, PDB can be triggered by a write to a register. No one says this write has to be done by software... so.. my hope is, DMA can be used. And DMA can be triggered by a pin..
    I hope this works.

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    Senior Member PaulStoffregen's Avatar
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    Oh, that is a crafty idea!

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    Definitely interesting if we can use a slave I2S DMA transfer register write to lock the ADC and DAC into the same sampling rate.

    If not then we then we would likely need to use a dynamically adjusted clock divider to minutely dither the BDC sampling rate to closely track the I2S transfer rates. This could be done using some sort of early/late feedback between ADC/DAC DMA completion time and the I2S DMA completion. Yuck!

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    Senior Member+ Frank B's Avatar
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    Yesterday, I tried it with AudioInputAnalogStereo, and for the moment, with an pin interrupt (from I2S Pin23) . It works.
    Looks like PDB needs three writes - not just one. Ok, no problem, I think this can be done with a minor loop for the DMA.

    Initially, I was thinking about modifying the Audio Library - Now, I think a simple "Addon", an additional "AudioTiming" Library is more simple and better. Let me see..

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    Senior Member+ Frank B's Avatar
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    Ok, triggering PDB with DMA (with DMA triggered by a pin) works!
    Now I can start writing the library. I'll open a new thread here.

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