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Thread: Extended Pin Numbering

  1. #26
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    Quote Originally Posted by finchamp View Post
    The purpose is the same as all open-sourcing: to save future developers time, effort, frustration, and to educate and lower the barrier to entry. If we can avoid it, why have a dozen people doing redundant work? That seems like a waste.
    (...)
    Changing gears, I'm leaning toward defining pins as port addresses per the datasheet (as stated earlier), and creating a spreadsheet -- similar to the PJRC pin reference card -- with color coded documentation of what each pin is capable of. Thoughts?
    I absolutely support this idea. Merging into the core is not really necessary, but the pure existence of a library style possibility to access all pins on custom pcbs is something I was already searching for***. In regard of the naming of these pins the port+number should be enough abstraction for the target audience. The more professional user can still define whatever he would like to, nobody will be forced to use this universal extension - as with all other solutions for common problems.

    ***Of course we could discuss a lot about that: Does building a custom teensy solution involve the ability to do the extensions on the software side to access the extra pins? To be honest, no, not for me without a lot of extra effort. But this discussion is objectless. I can make use of hundreds of abstracted software solutions to do fascinating things with this hardware without knowing a thing what really happens - so why not simply include another library and do a digitalWrite to Pin PTA27? Do it!

  2. #27
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    Quote Originally Posted by MichaelB View Post
    I absolutely support this idea. (...) I can make use of hundreds of abstracted software solutions to do fascinating things with this hardware without knowing a thing what really happens - so why not simply include another library and do a digitalWrite to Pin PTA27? Do it!
    Awesome! Glad you feel the same way.

  3. #28
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    Okay, this is VERY preliminary, and essentially untested. However, it DOES compile. I'm just hoping that this works the way it looks to, as I haven't spent as much time in the datasheet and libraries as most of you. This code belongs to Paul, so thanks again.

    You can refer to the extra pins numerically (PTA6 is "pin" 70; see file), or by their proper name (PTA6). I also added definitions to allow referring to Teensy-defined pins by their proper names. I have only added conditions for PTA6-8 for testing purposes, and only digital. Back up your core_pins.h, and replace it with the following (ONLY supports MK66!). I don't have my hardware yet, so somebody test this!

    Code:
    /* Extended pin definitions for standalone MK66 projects compatible with the Teensy 3.6 toolchain.
     * Based on Teensyduino Core Library - core_pins.h, V1.44
     * Copyright (c) 2017 PJRC.COM, LLC.
     
     * No affiliation with PJRC, no warranty or support expressed or implied.
     * https://forum.pjrc.com/threads/54114-Extended-Pin-Numbering
    */
    
    #ifndef _core_pins_h_
    #define _core_pins_h_
    
    #include "kinetis.h"
    #include "pins_arduino.h"
    
    #define HIGH		1
    #define LOW		0
    #define INPUT		0
    #define OUTPUT		1
    #define INPUT_PULLUP	2
    #define INPUT_PULLDOWN   3
    #define OUTPUT_OPENDRAIN 4
    #define INPUT_DISABLE   5
    #define LSBFIRST	0
    #define MSBFIRST	1
    #define _BV(n)		(1<<(n))
    #define CHANGE		4
    #define FALLING		2
    #define RISING		3
    
    
    #if defined(__MK66FX1M0__)
    #define CORE_NUM_TOTAL_PINS     97	// up from 64; double-check that these are all available
    #define CORE_NUM_DIGITAL        97	// up from 64; double-check that these are all available
    #define CORE_NUM_INTERRUPT      64	// need to research interrupt capabilities
    #define CORE_NUM_ANALOG         36  // double-check that these are all available
    #define CORE_NUM_PWM            22	// haven't looked at this
    #else error "Incorrect processor selected! This library only compatible with NXP MK66/Teensy 3.6!"  // Guarantees that this library extension is not used with any non-target processors
    #endif
    
    // These MAX_PIN_PORTx values have the highest Kinetis pin index
    // that is used for a given port.
    #define CORE_MAX_PIN_PORTA        29
    #define CORE_MAX_PIN_PORTB        23
    #define CORE_MAX_PIN_PORTC        19	// Up from 11
    #define CORE_MAX_PIN_PORTD        15
    #define CORE_MAX_PIN_PORTE        28	// Up from 26
    
    //---- Begin new definitions
    // DO NOT DEFINE PTA0-4
    // 64-69 already defined in pins_arduino.h
    #define PTA5			25
    #define PTA6			70 // new
    #define PTA7			71 // new
    #define PTA8			72 // new
    #define PTA9			73 // new
    #define PTA10			74 // new
    #define PTA11			75 // new
    #define PTA12			3
    #define PTA13			4
    #define PTA14			26
    #define PTA15			27
    #define PTA16			28
    #define PTA17			39
    #define PTA24			76 // new
    #define PTA25			77 // new
    #define PTA26			42
    #define PTA27			78 // new
    #define PTA28			40
    #define PTA29			41
    #define PTB0			16
    #define PTB1			17
    #define PTB2			19
    #define PTB3			18
    #define PTB4			49
    #define PTB5			50
    #define PTB6			79 // new
    #define PTB7			80 // new
    #define PTB8			81 // new
    #define PTB9			82 // new
    #define PTB10			31
    #define PTB11			32
    #define PTB16			0
    #define PTB17			1
    #define PTB18			29
    #define PTB19			30
    #define PTB20			43
    #define PTB21			46
    #define PTB22			44
    #define PTB23			45
    #define PTC0			15
    #define PTC1			22
    #define PTC2			23
    #define PTC3			9
    #define PTC4			10
    #define PTC5			13
    #define PTC6			11
    #define PTC7			12
    #define PTC8			35
    #define PTC9			36
    #define PTC10			37
    #define PTC11			38
    #define PTC12			83 // new
    #define PTC13			84 // new
    #define PTC14			85 // new
    #define PTC15			86 // new
    #define PTC16			87 // new
    #define PTC17			88 // new
    #define PTC18			89 // new
    #define PTC19			90 // new
    #define PTD0			2
    #define PTD1			14
    #define PTD2			7
    #define PTD3			8
    #define PTD4			6
    #define PTD5			20
    #define PTD6			21
    #define PTD7			5
    #define PTD8			47
    #define PTD9			48
    #define PTD10			85 // new
    #define PTD11			55
    #define PTD12			53
    #define PTD13			52
    #define PTD14			51
    #define PTD15			54
    //#define PTE0			N/A Built In SD
    //#define PTE1			N/A Built In SD
    //#define PTE2			N/A Built In SD
    //#define PTE3			N/A Built In SD
    //#define PTE4			N/A Built In SD
    //#define PTE5			N/A Built In SD
    #define PTE6			91 // new
    #define PTE7			92 // new
    #define PTE8			93 // new
    #define PTE9			94 // new
    #define PTE10			56
    #define PTE11			57
    #define PTE12			95 // new
    #define PTE24			33
    #define PTE25			34
    #define PTE26			24
    #define PTE27			96 // new
    #define PTE28			97 // new
    
    
    // PTA6
    #define CORE_PTA6_BIT		6
    #define CORE_PTA6_BITMASK	(1<<(CORE_PTA6_BIT))
    #define CORE_PTA6_PORTREG	GPIOA_PDOR
    #define CORE_PTA6_PORTSET	GPIOA_PSOR
    #define CORE_PTA6_PORTCLEAR	GPIOA_PCOR
    #define CORE_PTA6_DDRREG	GPIOA_PDDR
    #define CORE_PTA6_PINREG	GPIOA_PDIR
    #define CORE_PTA6_CONFIG	PORTA_PCR6
    
    // PTA7
    #define CORE_PTA7_BIT		7
    #define CORE_PTA7_BITMASK	(1<<(CORE_PTA7_BIT))
    #define CORE_PTA7_PORTREG	GPIOA_PDOR
    #define CORE_PTA7_PORTSET	GPIOA_PSOR
    #define CORE_PTA7_PORTCLEAR	GPIOA_PCOR
    #define CORE_PTA7_DDRREG	GPIOA_PDDR
    #define CORE_PTA7_PINREG	GPIOA_PDIR
    #define CORE_PTA7_CONFIG	PORTA_PCR7
    
    // PTA8
    #define CORE_PTA8_BIT		8
    #define CORE_PTA8_BITMASK	(1<<(CORE_PTA8_BIT))
    #define CORE_PTA8_PORTREG	GPIOA_PDOR
    #define CORE_PTA8_PORTSET	GPIOA_PSOR
    #define CORE_PTA8_PORTCLEAR	GPIOA_PCOR
    #define CORE_PTA8_DDRREG	GPIOA_PDDR
    #define CORE_PTA8_PINREG	GPIOA_PDIR
    #define CORE_PTA8_CONFIG	PORTA_PCR8
    
    
    //---- End new definitions
    
    
    #define CORE_PIN0_BIT		16
    #define CORE_PIN1_BIT		17
    #define CORE_PIN2_BIT		0
    #define CORE_PIN3_BIT		12
    #define CORE_PIN4_BIT		13
    #define CORE_PIN5_BIT		7
    #define CORE_PIN6_BIT		4
    #define CORE_PIN7_BIT		2
    #define CORE_PIN8_BIT		3
    #define CORE_PIN9_BIT		3
    #define CORE_PIN10_BIT		4
    #define CORE_PIN11_BIT		6
    #define CORE_PIN12_BIT		7
    #define CORE_PIN13_BIT		5
    #define CORE_PIN14_BIT		1
    #define CORE_PIN15_BIT		0
    #define CORE_PIN16_BIT		0
    #define CORE_PIN17_BIT		1
    #define CORE_PIN18_BIT		3
    #define CORE_PIN19_BIT		2
    #define CORE_PIN20_BIT		5
    #define CORE_PIN21_BIT		6
    #define CORE_PIN22_BIT		1
    #define CORE_PIN23_BIT		2
    #define CORE_PIN24_BIT		26
    #define CORE_PIN25_BIT		5
    #define CORE_PIN26_BIT		14
    #define CORE_PIN27_BIT		15
    #define CORE_PIN28_BIT		16
    #define CORE_PIN29_BIT		18
    #define CORE_PIN30_BIT		19
    #define CORE_PIN31_BIT		10
    #define CORE_PIN32_BIT		11
    #define CORE_PIN33_BIT		24
    #define CORE_PIN34_BIT		25
    #define CORE_PIN35_BIT		8
    #define CORE_PIN36_BIT		9
    #define CORE_PIN37_BIT		10
    #define CORE_PIN38_BIT		11
    #define CORE_PIN39_BIT		17
    #define CORE_PIN40_BIT		28
    #define CORE_PIN41_BIT		29
    #define CORE_PIN42_BIT		26
    #define CORE_PIN43_BIT		20
    #define CORE_PIN44_BIT		22
    #define CORE_PIN45_BIT		23
    #define CORE_PIN46_BIT		21
    #define CORE_PIN47_BIT		8
    #define CORE_PIN48_BIT		9
    #define CORE_PIN49_BIT		4
    #define CORE_PIN50_BIT		5
    #define CORE_PIN51_BIT		14
    #define CORE_PIN52_BIT		13
    #define CORE_PIN53_BIT		12
    #define CORE_PIN54_BIT		15
    #define CORE_PIN55_BIT		11
    #define CORE_PIN56_BIT		10
    #define CORE_PIN57_BIT		11
    #define CORE_PIN58_BIT		0
    #define CORE_PIN59_BIT		1
    #define CORE_PIN60_BIT		2
    #define CORE_PIN61_BIT		3
    #define CORE_PIN62_BIT		4
    #define CORE_PIN63_BIT		5
    
    #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))
    #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))
    #define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))
    #define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))
    #define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))
    #define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))
    #define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))
    #define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))
    #define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))
    #define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))
    #define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))
    #define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))
    #define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))
    #define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))
    #define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))
    #define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))
    #define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))
    #define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))
    #define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))
    #define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))
    #define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))
    #define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))
    #define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))
    #define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))
    #define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))
    #define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))
    #define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))
    #define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))
    #define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))
    #define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))
    #define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))
    #define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))
    #define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))
    #define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))
    #define CORE_PIN34_BITMASK	(1<<(CORE_PIN34_BIT))
    #define CORE_PIN35_BITMASK	(1<<(CORE_PIN35_BIT))
    #define CORE_PIN36_BITMASK	(1<<(CORE_PIN36_BIT))
    #define CORE_PIN37_BITMASK	(1<<(CORE_PIN37_BIT))
    #define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))
    #define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))
    #define CORE_PIN40_BITMASK	(1<<(CORE_PIN40_BIT))
    #define CORE_PIN41_BITMASK	(1<<(CORE_PIN41_BIT))
    #define CORE_PIN42_BITMASK	(1<<(CORE_PIN42_BIT))
    #define CORE_PIN43_BITMASK	(1<<(CORE_PIN43_BIT))
    #define CORE_PIN44_BITMASK	(1<<(CORE_PIN44_BIT))
    #define CORE_PIN45_BITMASK	(1<<(CORE_PIN45_BIT))
    #define CORE_PIN46_BITMASK	(1<<(CORE_PIN46_BIT))
    #define CORE_PIN47_BITMASK	(1<<(CORE_PIN47_BIT))
    #define CORE_PIN48_BITMASK	(1<<(CORE_PIN48_BIT))
    #define CORE_PIN49_BITMASK	(1<<(CORE_PIN49_BIT))
    #define CORE_PIN50_BITMASK	(1<<(CORE_PIN50_BIT))
    #define CORE_PIN51_BITMASK	(1<<(CORE_PIN51_BIT))
    #define CORE_PIN52_BITMASK	(1<<(CORE_PIN52_BIT))
    #define CORE_PIN53_BITMASK	(1<<(CORE_PIN53_BIT))
    #define CORE_PIN54_BITMASK	(1<<(CORE_PIN54_BIT))
    #define CORE_PIN55_BITMASK	(1<<(CORE_PIN55_BIT))
    #define CORE_PIN56_BITMASK	(1<<(CORE_PIN56_BIT))
    #define CORE_PIN57_BITMASK	(1<<(CORE_PIN57_BIT))
    #define CORE_PIN58_BITMASK	(1<<(CORE_PIN58_BIT))
    #define CORE_PIN59_BITMASK	(1<<(CORE_PIN59_BIT))
    #define CORE_PIN60_BITMASK	(1<<(CORE_PIN60_BIT))
    #define CORE_PIN61_BITMASK	(1<<(CORE_PIN61_BIT))
    #define CORE_PIN62_BITMASK	(1<<(CORE_PIN62_BIT))
    #define CORE_PIN63_BITMASK	(1<<(CORE_PIN63_BIT))
    
    
    #define CORE_PIN0_PORTREG	GPIOB_PDOR
    #define CORE_PIN1_PORTREG	GPIOB_PDOR
    #define CORE_PIN2_PORTREG	GPIOD_PDOR
    #define CORE_PIN3_PORTREG	GPIOA_PDOR
    #define CORE_PIN4_PORTREG	GPIOA_PDOR
    #define CORE_PIN5_PORTREG	GPIOD_PDOR
    #define CORE_PIN6_PORTREG	GPIOD_PDOR
    #define CORE_PIN7_PORTREG	GPIOD_PDOR
    #define CORE_PIN8_PORTREG	GPIOD_PDOR
    #define CORE_PIN9_PORTREG	GPIOC_PDOR
    #define CORE_PIN10_PORTREG	GPIOC_PDOR
    #define CORE_PIN11_PORTREG	GPIOC_PDOR
    #define CORE_PIN12_PORTREG	GPIOC_PDOR
    #define CORE_PIN13_PORTREG	GPIOC_PDOR
    #define CORE_PIN14_PORTREG	GPIOD_PDOR
    #define CORE_PIN15_PORTREG	GPIOC_PDOR
    #define CORE_PIN16_PORTREG	GPIOB_PDOR
    #define CORE_PIN17_PORTREG	GPIOB_PDOR
    #define CORE_PIN18_PORTREG	GPIOB_PDOR
    #define CORE_PIN19_PORTREG	GPIOB_PDOR
    #define CORE_PIN20_PORTREG	GPIOD_PDOR
    #define CORE_PIN21_PORTREG	GPIOD_PDOR
    #define CORE_PIN22_PORTREG	GPIOC_PDOR
    #define CORE_PIN23_PORTREG	GPIOC_PDOR
    #define CORE_PIN24_PORTREG	GPIOE_PDOR
    #define CORE_PIN25_PORTREG	GPIOA_PDOR
    #define CORE_PIN26_PORTREG	GPIOA_PDOR
    #define CORE_PIN27_PORTREG	GPIOA_PDOR
    #define CORE_PIN28_PORTREG	GPIOA_PDOR
    #define CORE_PIN29_PORTREG	GPIOB_PDOR
    #define CORE_PIN30_PORTREG	GPIOB_PDOR
    #define CORE_PIN31_PORTREG	GPIOB_PDOR
    #define CORE_PIN32_PORTREG	GPIOB_PDOR
    #define CORE_PIN33_PORTREG	GPIOE_PDOR
    #define CORE_PIN34_PORTREG	GPIOE_PDOR
    #define CORE_PIN35_PORTREG	GPIOC_PDOR
    #define CORE_PIN36_PORTREG	GPIOC_PDOR
    #define CORE_PIN37_PORTREG	GPIOC_PDOR
    #define CORE_PIN38_PORTREG	GPIOC_PDOR
    #define CORE_PIN39_PORTREG	GPIOA_PDOR
    #define CORE_PIN40_PORTREG	GPIOA_PDOR
    #define CORE_PIN41_PORTREG	GPIOA_PDOR
    #define CORE_PIN42_PORTREG	GPIOA_PDOR
    #define CORE_PIN43_PORTREG	GPIOB_PDOR
    #define CORE_PIN44_PORTREG	GPIOB_PDOR
    #define CORE_PIN45_PORTREG	GPIOB_PDOR
    #define CORE_PIN46_PORTREG	GPIOB_PDOR
    #define CORE_PIN47_PORTREG	GPIOD_PDOR
    #define CORE_PIN48_PORTREG	GPIOD_PDOR
    #define CORE_PIN49_PORTREG	GPIOB_PDOR
    #define CORE_PIN50_PORTREG	GPIOB_PDOR
    #define CORE_PIN51_PORTREG	GPIOD_PDOR
    #define CORE_PIN52_PORTREG	GPIOD_PDOR
    #define CORE_PIN53_PORTREG	GPIOD_PDOR
    #define CORE_PIN54_PORTREG	GPIOD_PDOR
    #define CORE_PIN55_PORTREG	GPIOD_PDOR
    #define CORE_PIN56_PORTREG	GPIOE_PDOR
    #define CORE_PIN57_PORTREG	GPIOE_PDOR
    #define CORE_PIN58_PORTREG	GPIOE_PDOR
    #define CORE_PIN59_PORTREG	GPIOE_PDOR
    #define CORE_PIN60_PORTREG	GPIOE_PDOR
    #define CORE_PIN61_PORTREG	GPIOE_PDOR
    #define CORE_PIN62_PORTREG	GPIOE_PDOR
    #define CORE_PIN63_PORTREG	GPIOE_PDOR
    
    #define CORE_PIN0_PORTSET	GPIOB_PSOR
    #define CORE_PIN1_PORTSET	GPIOB_PSOR
    #define CORE_PIN2_PORTSET	GPIOD_PSOR
    #define CORE_PIN3_PORTSET	GPIOA_PSOR
    #define CORE_PIN4_PORTSET	GPIOA_PSOR
    #define CORE_PIN5_PORTSET	GPIOD_PSOR
    #define CORE_PIN6_PORTSET	GPIOD_PSOR
    #define CORE_PIN7_PORTSET	GPIOD_PSOR
    #define CORE_PIN8_PORTSET	GPIOD_PSOR
    #define CORE_PIN9_PORTSET	GPIOC_PSOR
    #define CORE_PIN10_PORTSET	GPIOC_PSOR
    #define CORE_PIN11_PORTSET	GPIOC_PSOR
    #define CORE_PIN12_PORTSET	GPIOC_PSOR
    #define CORE_PIN13_PORTSET	GPIOC_PSOR
    #define CORE_PIN14_PORTSET	GPIOD_PSOR
    #define CORE_PIN15_PORTSET	GPIOC_PSOR
    #define CORE_PIN16_PORTSET	GPIOB_PSOR
    #define CORE_PIN17_PORTSET	GPIOB_PSOR
    #define CORE_PIN18_PORTSET	GPIOB_PSOR
    #define CORE_PIN19_PORTSET	GPIOB_PSOR
    #define CORE_PIN20_PORTSET	GPIOD_PSOR
    #define CORE_PIN21_PORTSET	GPIOD_PSOR
    #define CORE_PIN22_PORTSET	GPIOC_PSOR
    #define CORE_PIN23_PORTSET	GPIOC_PSOR
    #define CORE_PIN24_PORTSET	GPIOE_PSOR
    #define CORE_PIN25_PORTSET	GPIOA_PSOR
    #define CORE_PIN26_PORTSET	GPIOA_PSOR
    #define CORE_PIN27_PORTSET	GPIOA_PSOR
    #define CORE_PIN28_PORTSET	GPIOA_PSOR
    #define CORE_PIN29_PORTSET	GPIOB_PSOR
    #define CORE_PIN30_PORTSET	GPIOB_PSOR
    #define CORE_PIN31_PORTSET	GPIOB_PSOR
    #define CORE_PIN32_PORTSET	GPIOB_PSOR
    #define CORE_PIN33_PORTSET	GPIOE_PSOR
    #define CORE_PIN34_PORTSET	GPIOE_PSOR
    #define CORE_PIN35_PORTSET	GPIOC_PSOR
    #define CORE_PIN36_PORTSET	GPIOC_PSOR
    #define CORE_PIN37_PORTSET	GPIOC_PSOR
    #define CORE_PIN38_PORTSET	GPIOC_PSOR
    #define CORE_PIN39_PORTSET	GPIOA_PSOR
    #define CORE_PIN40_PORTSET	GPIOA_PSOR
    #define CORE_PIN41_PORTSET	GPIOA_PSOR
    #define CORE_PIN42_PORTSET	GPIOA_PSOR
    #define CORE_PIN43_PORTSET	GPIOB_PSOR
    #define CORE_PIN44_PORTSET	GPIOB_PSOR
    #define CORE_PIN45_PORTSET	GPIOB_PSOR
    #define CORE_PIN46_PORTSET	GPIOB_PSOR
    #define CORE_PIN47_PORTSET	GPIOD_PSOR
    #define CORE_PIN48_PORTSET	GPIOD_PSOR
    #define CORE_PIN49_PORTSET	GPIOB_PSOR
    #define CORE_PIN50_PORTSET	GPIOB_PSOR
    #define CORE_PIN51_PORTSET	GPIOD_PSOR
    #define CORE_PIN52_PORTSET	GPIOD_PSOR
    #define CORE_PIN53_PORTSET	GPIOD_PSOR
    #define CORE_PIN54_PORTSET	GPIOD_PSOR
    #define CORE_PIN55_PORTSET	GPIOD_PSOR
    #define CORE_PIN56_PORTSET	GPIOE_PSOR
    #define CORE_PIN57_PORTSET	GPIOE_PSOR
    #define CORE_PIN58_PORTSET	GPIOE_PSOR
    #define CORE_PIN59_PORTSET	GPIOE_PSOR
    #define CORE_PIN60_PORTSET	GPIOE_PSOR
    #define CORE_PIN61_PORTSET	GPIOE_PSOR
    #define CORE_PIN62_PORTSET	GPIOE_PSOR
    #define CORE_PIN63_PORTSET	GPIOE_PSOR
    
    #define CORE_PIN0_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN1_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN2_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN3_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN4_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN5_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN6_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN7_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN8_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN9_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN10_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN11_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN12_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN13_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN14_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN15_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN16_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN17_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN18_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN19_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN20_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN21_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN22_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN23_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN24_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN25_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN26_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN27_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN28_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN29_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN30_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN31_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN32_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN33_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN34_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN35_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN36_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN37_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN38_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN39_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN40_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN41_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN42_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN43_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN44_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN45_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN46_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN47_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN48_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN49_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN50_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN51_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN52_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN53_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN54_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN55_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN56_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN57_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN58_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN59_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN60_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN61_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN62_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN63_PORTCLEAR	GPIOE_PCOR
    
    #define CORE_PIN0_DDRREG	GPIOB_PDDR
    #define CORE_PIN1_DDRREG	GPIOB_PDDR
    #define CORE_PIN2_DDRREG	GPIOD_PDDR
    #define CORE_PIN3_DDRREG	GPIOA_PDDR
    #define CORE_PIN4_DDRREG	GPIOA_PDDR
    #define CORE_PIN5_DDRREG	GPIOD_PDDR
    #define CORE_PIN6_DDRREG	GPIOD_PDDR
    #define CORE_PIN7_DDRREG	GPIOD_PDDR
    #define CORE_PIN8_DDRREG	GPIOD_PDDR
    #define CORE_PIN9_DDRREG	GPIOC_PDDR
    #define CORE_PIN10_DDRREG	GPIOC_PDDR
    #define CORE_PIN11_DDRREG	GPIOC_PDDR
    #define CORE_PIN12_DDRREG	GPIOC_PDDR
    #define CORE_PIN13_DDRREG	GPIOC_PDDR
    #define CORE_PIN14_DDRREG	GPIOD_PDDR
    #define CORE_PIN15_DDRREG	GPIOC_PDDR
    #define CORE_PIN16_DDRREG	GPIOB_PDDR
    #define CORE_PIN17_DDRREG	GPIOB_PDDR
    #define CORE_PIN18_DDRREG	GPIOB_PDDR
    #define CORE_PIN19_DDRREG	GPIOB_PDDR
    #define CORE_PIN20_DDRREG	GPIOD_PDDR
    #define CORE_PIN21_DDRREG	GPIOD_PDDR
    #define CORE_PIN22_DDRREG	GPIOC_PDDR
    #define CORE_PIN23_DDRREG	GPIOC_PDDR
    #define CORE_PIN24_DDRREG	GPIOE_PDDR
    #define CORE_PIN25_DDRREG	GPIOA_PDDR
    #define CORE_PIN26_DDRREG	GPIOA_PDDR
    #define CORE_PIN27_DDRREG	GPIOA_PDDR
    #define CORE_PIN28_DDRREG	GPIOA_PDDR
    #define CORE_PIN29_DDRREG	GPIOB_PDDR
    #define CORE_PIN30_DDRREG	GPIOB_PDDR
    #define CORE_PIN31_DDRREG	GPIOB_PDDR
    #define CORE_PIN32_DDRREG	GPIOB_PDDR
    #define CORE_PIN33_DDRREG	GPIOE_PDDR
    #define CORE_PIN34_DDRREG	GPIOE_PDDR
    #define CORE_PIN35_DDRREG	GPIOC_PDDR
    #define CORE_PIN36_DDRREG	GPIOC_PDDR
    #define CORE_PIN37_DDRREG	GPIOC_PDDR
    #define CORE_PIN38_DDRREG	GPIOC_PDDR
    #define CORE_PIN39_DDRREG	GPIOA_PDDR
    #define CORE_PIN40_DDRREG	GPIOA_PDDR
    #define CORE_PIN41_DDRREG	GPIOA_PDDR
    #define CORE_PIN42_DDRREG	GPIOA_PDDR
    #define CORE_PIN43_DDRREG	GPIOB_PDDR
    #define CORE_PIN44_DDRREG	GPIOB_PDDR
    #define CORE_PIN45_DDRREG	GPIOB_PDDR
    #define CORE_PIN46_DDRREG	GPIOB_PDDR
    #define CORE_PIN47_DDRREG	GPIOD_PDDR
    #define CORE_PIN48_DDRREG	GPIOD_PDDR
    #define CORE_PIN49_DDRREG	GPIOB_PDDR
    #define CORE_PIN50_DDRREG	GPIOB_PDDR
    #define CORE_PIN51_DDRREG	GPIOD_PDDR
    #define CORE_PIN52_DDRREG	GPIOD_PDDR
    #define CORE_PIN53_DDRREG	GPIOD_PDDR
    #define CORE_PIN54_DDRREG	GPIOD_PDDR
    #define CORE_PIN55_DDRREG	GPIOD_PDDR
    #define CORE_PIN56_DDRREG	GPIOE_PDDR
    #define CORE_PIN57_DDRREG	GPIOE_PDDR
    #define CORE_PIN58_DDRREG	GPIOE_PDDR
    #define CORE_PIN59_DDRREG	GPIOE_PDDR
    #define CORE_PIN60_DDRREG	GPIOE_PDDR
    #define CORE_PIN61_DDRREG	GPIOE_PDDR
    #define CORE_PIN62_DDRREG	GPIOE_PDDR
    #define CORE_PIN63_DDRREG	GPIOE_PDDR
    
    #define CORE_PIN0_PINREG	GPIOB_PDIR
    #define CORE_PIN1_PINREG	GPIOB_PDIR
    #define CORE_PIN2_PINREG	GPIOD_PDIR
    #define CORE_PIN3_PINREG	GPIOA_PDIR
    #define CORE_PIN4_PINREG	GPIOA_PDIR
    #define CORE_PIN5_PINREG	GPIOD_PDIR
    #define CORE_PIN6_PINREG	GPIOD_PDIR
    #define CORE_PIN7_PINREG	GPIOD_PDIR
    #define CORE_PIN8_PINREG	GPIOD_PDIR
    #define CORE_PIN9_PINREG	GPIOC_PDIR
    #define CORE_PIN10_PINREG	GPIOC_PDIR
    #define CORE_PIN11_PINREG	GPIOC_PDIR
    #define CORE_PIN12_PINREG	GPIOC_PDIR
    #define CORE_PIN13_PINREG	GPIOC_PDIR
    #define CORE_PIN14_PINREG	GPIOD_PDIR
    #define CORE_PIN15_PINREG	GPIOC_PDIR
    #define CORE_PIN16_PINREG	GPIOB_PDIR
    #define CORE_PIN17_PINREG	GPIOB_PDIR
    #define CORE_PIN18_PINREG	GPIOB_PDIR
    #define CORE_PIN19_PINREG	GPIOB_PDIR
    #define CORE_PIN20_PINREG	GPIOD_PDIR
    #define CORE_PIN21_PINREG	GPIOD_PDIR
    #define CORE_PIN22_PINREG	GPIOC_PDIR
    #define CORE_PIN23_PINREG	GPIOC_PDIR
    #define CORE_PIN24_PINREG	GPIOE_PDIR
    #define CORE_PIN25_PINREG	GPIOA_PDIR
    #define CORE_PIN26_PINREG	GPIOA_PDIR
    #define CORE_PIN27_PINREG	GPIOA_PDIR
    #define CORE_PIN28_PINREG	GPIOA_PDIR
    #define CORE_PIN29_PINREG	GPIOB_PDIR
    #define CORE_PIN30_PINREG	GPIOB_PDIR
    #define CORE_PIN31_PINREG	GPIOB_PDIR
    #define CORE_PIN32_PINREG	GPIOB_PDIR
    #define CORE_PIN33_PINREG	GPIOE_PDIR
    #define CORE_PIN34_PINREG	GPIOE_PDIR
    #define CORE_PIN35_PINREG	GPIOC_PDIR
    #define CORE_PIN36_PINREG	GPIOC_PDIR
    #define CORE_PIN37_PINREG	GPIOC_PDIR
    #define CORE_PIN38_PINREG	GPIOC_PDIR
    #define CORE_PIN39_PINREG	GPIOA_PDIR
    #define CORE_PIN40_PINREG	GPIOA_PDIR
    #define CORE_PIN41_PINREG	GPIOA_PDIR
    #define CORE_PIN42_PINREG	GPIOA_PDIR
    #define CORE_PIN43_PINREG	GPIOB_PDIR
    #define CORE_PIN44_PINREG	GPIOB_PDIR
    #define CORE_PIN45_PINREG	GPIOB_PDIR
    #define CORE_PIN46_PINREG	GPIOB_PDIR
    #define CORE_PIN47_PINREG	GPIOD_PDIR
    #define CORE_PIN48_PINREG	GPIOD_PDIR
    #define CORE_PIN49_PINREG	GPIOB_PDIR
    #define CORE_PIN50_PINREG	GPIOB_PDIR
    #define CORE_PIN51_PINREG	GPIOD_PDIR
    #define CORE_PIN52_PINREG	GPIOD_PDIR
    #define CORE_PIN53_PINREG	GPIOD_PDIR
    #define CORE_PIN54_PINREG	GPIOD_PDIR
    #define CORE_PIN55_PINREG	GPIOD_PDIR
    #define CORE_PIN56_PINREG	GPIOE_PDIR
    #define CORE_PIN57_PINREG	GPIOE_PDIR
    #define CORE_PIN58_PINREG	GPIOE_PDIR
    #define CORE_PIN59_PINREG	GPIOE_PDIR
    #define CORE_PIN60_PINREG	GPIOE_PDIR
    #define CORE_PIN61_PINREG	GPIOE_PDIR
    #define CORE_PIN62_PINREG	GPIOE_PDIR
    #define CORE_PIN63_PINREG	GPIOE_PDIR
    
    #define CORE_PIN0_CONFIG	PORTB_PCR16
    #define CORE_PIN1_CONFIG	PORTB_PCR17
    #define CORE_PIN2_CONFIG	PORTD_PCR0
    #define CORE_PIN3_CONFIG	PORTA_PCR12
    #define CORE_PIN4_CONFIG	PORTA_PCR13
    #define CORE_PIN5_CONFIG	PORTD_PCR7
    #define CORE_PIN6_CONFIG	PORTD_PCR4
    #define CORE_PIN7_CONFIG	PORTD_PCR2
    #define CORE_PIN8_CONFIG	PORTD_PCR3
    #define CORE_PIN9_CONFIG	PORTC_PCR3
    #define CORE_PIN10_CONFIG	PORTC_PCR4
    #define CORE_PIN11_CONFIG	PORTC_PCR6
    #define CORE_PIN12_CONFIG	PORTC_PCR7
    #define CORE_PIN13_CONFIG	PORTC_PCR5
    #define CORE_PIN14_CONFIG	PORTD_PCR1
    #define CORE_PIN15_CONFIG	PORTC_PCR0
    #define CORE_PIN16_CONFIG	PORTB_PCR0
    #define CORE_PIN17_CONFIG	PORTB_PCR1
    #define CORE_PIN18_CONFIG	PORTB_PCR3
    #define CORE_PIN19_CONFIG	PORTB_PCR2
    #define CORE_PIN20_CONFIG	PORTD_PCR5
    #define CORE_PIN21_CONFIG	PORTD_PCR6
    #define CORE_PIN22_CONFIG	PORTC_PCR1
    #define CORE_PIN23_CONFIG	PORTC_PCR2
    #define CORE_PIN24_CONFIG	PORTE_PCR26
    #define CORE_PIN25_CONFIG	PORTA_PCR5
    #define CORE_PIN26_CONFIG	PORTA_PCR14
    #define CORE_PIN27_CONFIG	PORTA_PCR15
    #define CORE_PIN28_CONFIG	PORTA_PCR16
    #define CORE_PIN29_CONFIG	PORTB_PCR18
    #define CORE_PIN30_CONFIG	PORTB_PCR19
    #define CORE_PIN31_CONFIG	PORTB_PCR10
    #define CORE_PIN32_CONFIG	PORTB_PCR11
    #define CORE_PIN33_CONFIG	PORTE_PCR24
    #define CORE_PIN34_CONFIG	PORTE_PCR25
    #define CORE_PIN35_CONFIG	PORTC_PCR8
    #define CORE_PIN36_CONFIG	PORTC_PCR9
    #define CORE_PIN37_CONFIG	PORTC_PCR10
    #define CORE_PIN38_CONFIG	PORTC_PCR11
    #define CORE_PIN39_CONFIG	PORTA_PCR17
    #define CORE_PIN40_CONFIG	PORTA_PCR28
    #define CORE_PIN41_CONFIG	PORTA_PCR29
    #define CORE_PIN42_CONFIG	PORTA_PCR26
    #define CORE_PIN43_CONFIG	PORTB_PCR20
    #define CORE_PIN44_CONFIG	PORTB_PCR22
    #define CORE_PIN45_CONFIG	PORTB_PCR23
    #define CORE_PIN46_CONFIG	PORTB_PCR21
    #define CORE_PIN47_CONFIG	PORTD_PCR8
    #define CORE_PIN48_CONFIG	PORTD_PCR9
    #define CORE_PIN49_CONFIG	PORTB_PCR4
    #define CORE_PIN50_CONFIG	PORTB_PCR5
    #define CORE_PIN51_CONFIG	PORTD_PCR14
    #define CORE_PIN52_CONFIG	PORTD_PCR13
    #define CORE_PIN53_CONFIG	PORTD_PCR12
    #define CORE_PIN54_CONFIG	PORTD_PCR15
    #define CORE_PIN55_CONFIG	PORTD_PCR11
    #define CORE_PIN56_CONFIG	PORTE_PCR10
    #define CORE_PIN57_CONFIG	PORTE_PCR11
    #define CORE_PIN58_CONFIG	PORTE_PCR0
    #define CORE_PIN59_CONFIG	PORTE_PCR1
    #define CORE_PIN60_CONFIG	PORTE_PCR2
    #define CORE_PIN61_CONFIG	PORTE_PCR3
    #define CORE_PIN62_CONFIG	PORTE_PCR4
    #define CORE_PIN63_CONFIG	PORTE_PCR5
    
    #define CORE_ADC0_PIN		14
    #define CORE_ADC1_PIN		15
    #define CORE_ADC2_PIN		16
    #define CORE_ADC3_PIN		17
    #define CORE_ADC4_PIN		18
    #define CORE_ADC5_PIN		19
    #define CORE_ADC6_PIN		20
    #define CORE_ADC7_PIN		21
    #define CORE_ADC8_PIN		22
    #define CORE_ADC9_PIN		23
    #define CORE_ADC10_PIN		64
    #define CORE_ADC11_PIN		65
    #define CORE_ADC12_PIN		31
    #define CORE_ADC13_PIN		32
    #define CORE_ADC14_PIN		33
    #define CORE_ADC15_PIN		34
    #define CORE_ADC16_PIN		35
    #define CORE_ADC17_PIN		36
    #define CORE_ADC18_PIN		37
    #define CORE_ADC19_PIN		38
    #define CORE_ADC20_PIN		39
    #define CORE_ADC21_PIN		66
    #define CORE_ADC22_PIN		67
    #define CORE_ADC23_PIN		49
    #define CORE_ADC24_PIN		50
    #define CORE_ADC25_PIN		68
    #define CORE_ADC26_PIN		69
    
    #define CORE_RXD0_PIN		0
    #define CORE_TXD0_PIN		1
    #define CORE_RXD1_PIN		9
    #define CORE_TXD1_PIN		10
    #define CORE_RXD2_PIN		7
    #define CORE_TXD2_PIN		8
    #define CORE_RXD3_PIN		31
    #define CORE_TXD3_PIN		32
    #define CORE_RXD4_PIN		34
    #define CORE_TXD4_PIN		33
    
    #define CORE_INT0_PIN		0
    #define CORE_INT1_PIN		1
    #define CORE_INT2_PIN		2
    #define CORE_INT3_PIN		3
    #define CORE_INT4_PIN		4
    #define CORE_INT5_PIN		5
    #define CORE_INT6_PIN		6
    #define CORE_INT7_PIN		7
    #define CORE_INT8_PIN		8
    #define CORE_INT9_PIN		9
    #define CORE_INT10_PIN		10
    #define CORE_INT11_PIN		11
    #define CORE_INT12_PIN		12
    #define CORE_INT13_PIN		13
    #define CORE_INT14_PIN		14
    #define CORE_INT15_PIN		15
    #define CORE_INT16_PIN		16
    #define CORE_INT17_PIN		17
    #define CORE_INT18_PIN		18
    #define CORE_INT19_PIN		19
    #define CORE_INT20_PIN		20
    #define CORE_INT21_PIN		21
    #define CORE_INT22_PIN		22
    #define CORE_INT23_PIN		23
    #define CORE_INT24_PIN		24
    #define CORE_INT25_PIN		25
    #define CORE_INT26_PIN		26
    #define CORE_INT27_PIN		27
    #define CORE_INT28_PIN		28
    #define CORE_INT29_PIN		29
    #define CORE_INT30_PIN		30
    #define CORE_INT31_PIN		31
    #define CORE_INT32_PIN		32
    #define CORE_INT33_PIN		33
    #define CORE_INT34_PIN		34
    #define CORE_INT35_PIN		35
    #define CORE_INT36_PIN		36
    #define CORE_INT37_PIN		37
    #define CORE_INT38_PIN		38
    #define CORE_INT39_PIN		39
    #define CORE_INT40_PIN		40
    #define CORE_INT41_PIN		41
    #define CORE_INT42_PIN		42
    #define CORE_INT43_PIN		43
    #define CORE_INT44_PIN		44
    #define CORE_INT45_PIN		45
    #define CORE_INT46_PIN		46
    #define CORE_INT47_PIN		47
    #define CORE_INT48_PIN		48
    #define CORE_INT49_PIN		49
    #define CORE_INT50_PIN		50
    #define CORE_INT51_PIN		51
    #define CORE_INT52_PIN		52
    #define CORE_INT53_PIN		53
    #define CORE_INT54_PIN		54
    #define CORE_INT55_PIN		55
    #define CORE_INT56_PIN		56
    #define CORE_INT57_PIN		57
    #define CORE_INT58_PIN		58
    #define CORE_INT59_PIN		59
    #define CORE_INT60_PIN		60
    #define CORE_INT61_PIN		61
    #define CORE_INT62_PIN		62
    #define CORE_INT63_PIN		63
    #define CORE_INT_EVERY_PIN	1
    
    
    
    
    
    #define CORE_FTM0_CH0_PIN	22
    #define CORE_FTM0_CH1_PIN	23
    #define CORE_FTM0_CH2_PIN	 9
    #define CORE_FTM0_CH3_PIN	10
    #define CORE_FTM0_CH4_PIN	 6
    #define CORE_FTM0_CH5_PIN	20
    #define CORE_FTM0_CH6_PIN	21
    #define CORE_FTM0_CH7_PIN	 5
    #define CORE_FTM1_CH0_PIN	 3
    #define CORE_FTM1_CH1_PIN	 4
    #define CORE_FTM2_CH0_PIN	29
    #define CORE_FTM2_CH1_PIN	30
    #define CORE_FTM3_CH0_PIN	 2
    #define CORE_FTM3_CH1_PIN	14
    #define CORE_FTM3_CH2_PIN	 7
    #define CORE_FTM3_CH3_PIN	 8
    #define CORE_FTM3_CH4_PIN	35
    #define CORE_FTM3_CH5_PIN	36
    #define CORE_FTM3_CH6_PIN	37
    #define CORE_FTM3_CH7_PIN	38
    #define CORE_TPM1_CH0_PIN	16
    #define CORE_TPM1_CH1_PIN	17
    
    
    
    #ifdef __cplusplus
    extern "C" {
    #endif
    
    void digitalWrite(uint8_t pin, uint8_t val);
    static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused));
    static inline void digitalWriteFast(uint8_t pin, uint8_t val)
    {
    	if (__builtin_constant_p(pin)) {
    		if (val) {
    			if (pin == 0) {
    				CORE_PIN0_PORTSET = CORE_PIN0_BITMASK;
    			} else if (pin == 1) {
    				CORE_PIN1_PORTSET = CORE_PIN1_BITMASK;
    			} else if (pin == 2) {
    				CORE_PIN2_PORTSET = CORE_PIN2_BITMASK;
    			} else if (pin == 3) {
    				CORE_PIN3_PORTSET = CORE_PIN3_BITMASK;
    			} else if (pin == 4) {
    				CORE_PIN4_PORTSET = CORE_PIN4_BITMASK;
    			} else if (pin == 5) {
    				CORE_PIN5_PORTSET = CORE_PIN5_BITMASK;
    			} else if (pin == 6) {
    				CORE_PIN6_PORTSET = CORE_PIN6_BITMASK;
    			} else if (pin == 7) {
    				CORE_PIN7_PORTSET = CORE_PIN7_BITMASK;
    			} else if (pin == 8) {
    				CORE_PIN8_PORTSET = CORE_PIN8_BITMASK;
    			} else if (pin == 9) {
    				CORE_PIN9_PORTSET = CORE_PIN9_BITMASK;
    			} else if (pin == 10) {
    				CORE_PIN10_PORTSET = CORE_PIN10_BITMASK;
    			} else if (pin == 11) {
    				CORE_PIN11_PORTSET = CORE_PIN11_BITMASK;
    			} else if (pin == 12) {
    				CORE_PIN12_PORTSET = CORE_PIN12_BITMASK;
    			} else if (pin == 13) {
    				CORE_PIN13_PORTSET = CORE_PIN13_BITMASK;
    			} else if (pin == 14) {
    				CORE_PIN14_PORTSET = CORE_PIN14_BITMASK;
    			} else if (pin == 15) {
    				CORE_PIN15_PORTSET = CORE_PIN15_BITMASK;
    			} else if (pin == 16) {
    				CORE_PIN16_PORTSET = CORE_PIN16_BITMASK;
    			} else if (pin == 17) {
    				CORE_PIN17_PORTSET = CORE_PIN17_BITMASK;
    			} else if (pin == 18) {
    				CORE_PIN18_PORTSET = CORE_PIN18_BITMASK;
    			} else if (pin == 19) {
    				CORE_PIN19_PORTSET = CORE_PIN19_BITMASK;
    			} else if (pin == 20) {
    				CORE_PIN20_PORTSET = CORE_PIN20_BITMASK;
    			} else if (pin == 21) {
    				CORE_PIN21_PORTSET = CORE_PIN21_BITMASK;
    			} else if (pin == 22) {
    				CORE_PIN22_PORTSET = CORE_PIN22_BITMASK;
    			} else if (pin == 23) {
    				CORE_PIN23_PORTSET = CORE_PIN23_BITMASK;
    			} else if (pin == 24) {
    				CORE_PIN24_PORTSET = CORE_PIN24_BITMASK;
    			} else if (pin == 25) {
    				CORE_PIN25_PORTSET = CORE_PIN25_BITMASK;
    			} else if (pin == 26) {
    				CORE_PIN26_PORTSET = CORE_PIN26_BITMASK;
    			}
    			#if defined(CORE_PIN27_PORTSET)
    			  else if (pin == 27) {
    				CORE_PIN27_PORTSET = CORE_PIN27_BITMASK;
    			} else if (pin == 28) {
    				CORE_PIN28_PORTSET = CORE_PIN28_BITMASK;
    			} else if (pin == 29) {
    				CORE_PIN29_PORTSET = CORE_PIN29_BITMASK;
    			} else if (pin == 30) {
    				CORE_PIN30_PORTSET = CORE_PIN30_BITMASK;
    			} else if (pin == 31) {
    				CORE_PIN31_PORTSET = CORE_PIN31_BITMASK;
    			} else if (pin == 32) {
    				CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;
    			} else if (pin == 33) {
    				CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;
    			}
    			#endif
    			#if defined(CORE_PIN34_PORTSET)
    			  else if (pin == 34) {
    				CORE_PIN34_PORTSET = CORE_PIN34_BITMASK;
    			} else if (pin == 35) {
    				CORE_PIN35_PORTSET = CORE_PIN35_BITMASK;
    			} else if (pin == 36) {
    				CORE_PIN36_PORTSET = CORE_PIN36_BITMASK;
    			} else if (pin == 37) {
    				CORE_PIN37_PORTSET = CORE_PIN37_BITMASK;
    			} else if (pin == 38) {
    				CORE_PIN38_PORTSET = CORE_PIN38_BITMASK;
    			} else if (pin == 39) {
    				CORE_PIN39_PORTSET = CORE_PIN39_BITMASK;
    			} else if (pin == 40) {
    				CORE_PIN40_PORTSET = CORE_PIN40_BITMASK;
    			} else if (pin == 41) {
    				CORE_PIN41_PORTSET = CORE_PIN41_BITMASK;
    			} else if (pin == 42) {
    				CORE_PIN42_PORTSET = CORE_PIN42_BITMASK;
    			} else if (pin == 43) {
    				CORE_PIN43_PORTSET = CORE_PIN43_BITMASK;
    			} else if (pin == 44) {
    				CORE_PIN44_PORTSET = CORE_PIN44_BITMASK;
    			} else if (pin == 45) {
    				CORE_PIN45_PORTSET = CORE_PIN45_BITMASK;
    			} else if (pin == 46) {
    				CORE_PIN46_PORTSET = CORE_PIN46_BITMASK;
    			} else if (pin == 47) {
    				CORE_PIN47_PORTSET = CORE_PIN47_BITMASK;
    			} else if (pin == 48) {
    				CORE_PIN48_PORTSET = CORE_PIN48_BITMASK;
    			} else if (pin == 49) {
    				CORE_PIN49_PORTSET = CORE_PIN49_BITMASK;
    			} else if (pin == 50) {
    				CORE_PIN50_PORTSET = CORE_PIN50_BITMASK;
    			} else if (pin == 51) {
    				CORE_PIN51_PORTSET = CORE_PIN51_BITMASK;
    			} else if (pin == 52) {
    				CORE_PIN52_PORTSET = CORE_PIN52_BITMASK;
    			} else if (pin == 53) {
    				CORE_PIN53_PORTSET = CORE_PIN53_BITMASK;
    			} else if (pin == 54) {
    				CORE_PIN54_PORTSET = CORE_PIN54_BITMASK;
    			} else if (pin == 55) {
    				CORE_PIN55_PORTSET = CORE_PIN55_BITMASK;
    			} else if (pin == 56) {
    				CORE_PIN56_PORTSET = CORE_PIN56_BITMASK;
    			} else if (pin == 57) {
    				CORE_PIN57_PORTSET = CORE_PIN57_BITMASK;
    			} else if (pin == 58) {
    				CORE_PIN58_PORTSET = CORE_PIN58_BITMASK;
    			} else if (pin == 59) {
    				CORE_PIN59_PORTSET = CORE_PIN59_BITMASK;
    			} else if (pin == 60) {
    				CORE_PIN60_PORTSET = CORE_PIN60_BITMASK;
    			} else if (pin == 61) {
    				CORE_PIN61_PORTSET = CORE_PIN61_BITMASK;
    			} else if (pin == 62) {
    				CORE_PIN62_PORTSET = CORE_PIN62_BITMASK;
    			} else if (pin == 63) {
    				CORE_PIN63_PORTSET = CORE_PIN63_BITMASK;
    			} else if (pin == PTA6) {
    				CORE_PTA6_PORTSET = CORE_PTA6_BITMASK;
    			}
    			#endif
    		} else {
    			if (pin == 0) {
    				CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;
    			} else if (pin == 1) {
    				CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK;
    			} else if (pin == 2) {
    				CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK;
    			} else if (pin == 3) {
    				CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK;
    			} else if (pin == 4) {
    				CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK;
    			} else if (pin == 5) {
    				CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK;
    			} else if (pin == 6) {
    				CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK;
    			} else if (pin == 7) {
    				CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK;
    			} else if (pin == 8) {
    				CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK;
    			} else if (pin == 9) {
    				CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK;
    			} else if (pin == 10) {
    				CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK;
    			} else if (pin == 11) {
    				CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK;
    			} else if (pin == 12) {
    				CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK;
    			} else if (pin == 13) {
    				CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK;
    			} else if (pin == 14) {
    				CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK;
    			} else if (pin == 15) {
    				CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK;
    			} else if (pin == 16) {
    				CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK;
    			} else if (pin == 17) {
    				CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK;
    			} else if (pin == 18) {
    				CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK;
    			} else if (pin == 19) {
    				CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK;
    			} else if (pin == 20) {
    				CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK;
    			} else if (pin == 21) {
    				CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK;
    			} else if (pin == 22) {
    				CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK;
    			} else if (pin == 23) {
    				CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK;
    			} else if (pin == 24) {
    				CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK;
    			} else if (pin == 25) {
    				CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK;
    			} else if (pin == 26) {
    				CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK;
    			}
    			#if defined(CORE_PIN27_PORTCLEAR)
    			  else if (pin == 27) {
    				CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK;
    			} else if (pin == 28) {
    				CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK;
    			} else if (pin == 29) {
    				CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK;
    			} else if (pin == 30) {
    				CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK;
    			} else if (pin == 31) {
    				CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK;
    			} else if (pin == 32) {
    				CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;
    			} else if (pin == 33) {
    				CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;
    			}
    			#endif
    			#if defined(CORE_PIN34_PORTCLEAR)
    			  else if (pin == 34) {
    				CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK;
    			} else if (pin == 35) {
    				CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK;
    			} else if (pin == 36) {
    				CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK;
    			} else if (pin == 37) {
    				CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK;
    			} else if (pin == 38) {
    				CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK;
    			} else if (pin == 39) {
    				CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK;
    			} else if (pin == 40) {
    				CORE_PIN40_PORTCLEAR = CORE_PIN40_BITMASK;
    			} else if (pin == 41) {
    				CORE_PIN41_PORTCLEAR = CORE_PIN41_BITMASK;
    			} else if (pin == 42) {
    				CORE_PIN42_PORTCLEAR = CORE_PIN42_BITMASK;
    			} else if (pin == 43) {
    				CORE_PIN43_PORTCLEAR = CORE_PIN43_BITMASK;
    			} else if (pin == 44) {
    				CORE_PIN44_PORTCLEAR = CORE_PIN44_BITMASK;
    			} else if (pin == 45) {
    				CORE_PIN45_PORTCLEAR = CORE_PIN45_BITMASK;
    			} else if (pin == 46) {
    				CORE_PIN46_PORTCLEAR = CORE_PIN46_BITMASK;
    			} else if (pin == 47) {
    				CORE_PIN47_PORTCLEAR = CORE_PIN47_BITMASK;
    			} else if (pin == 48) {
    				CORE_PIN48_PORTCLEAR = CORE_PIN48_BITMASK;
    			} else if (pin == 49) {
    				CORE_PIN49_PORTCLEAR = CORE_PIN49_BITMASK;
    			} else if (pin == 50) {
    				CORE_PIN50_PORTCLEAR = CORE_PIN50_BITMASK;
    			} else if (pin == 51) {
    				CORE_PIN51_PORTCLEAR = CORE_PIN51_BITMASK;
    			} else if (pin == 52) {
    				CORE_PIN52_PORTCLEAR = CORE_PIN52_BITMASK;
    			} else if (pin == 53) {
    				CORE_PIN53_PORTCLEAR = CORE_PIN53_BITMASK;
    			} else if (pin == 54) {
    				CORE_PIN54_PORTCLEAR = CORE_PIN54_BITMASK;
    			} else if (pin == 55) {
    				CORE_PIN55_PORTCLEAR = CORE_PIN55_BITMASK;
    			} else if (pin == 56) {
    				CORE_PIN56_PORTCLEAR = CORE_PIN56_BITMASK;
    			} else if (pin == 57) {
    				CORE_PIN57_PORTCLEAR = CORE_PIN57_BITMASK;
    			} else if (pin == 58) {
    				CORE_PIN58_PORTCLEAR = CORE_PIN58_BITMASK;
    			} else if (pin == 59) {
    				CORE_PIN59_PORTCLEAR = CORE_PIN59_BITMASK;
    			} else if (pin == 60) {
    				CORE_PIN60_PORTCLEAR = CORE_PIN60_BITMASK;
    			} else if (pin == 61) {
    				CORE_PIN61_PORTCLEAR = CORE_PIN61_BITMASK;
    			} else if (pin == 62) {
    				CORE_PIN62_PORTCLEAR = CORE_PIN62_BITMASK;
    			} else if (pin == 63) {
    				CORE_PIN63_PORTCLEAR = CORE_PIN63_BITMASK;
    			} else if (pin == PTA6) {
    				CORE_PTA6_PORTCLEAR = CORE_PTA6_BITMASK;
    			} else if (pin == PTA7) {
    				CORE_PTA7_PORTCLEAR = CORE_PTA7_BITMASK;
    			} else if (pin == PTA8) {
    				CORE_PTA8_PORTCLEAR = CORE_PTA8_BITMASK;
    			}
    			#endif
    		}
    	} else {
    		if (val) {
    			*portSetRegister(pin) = digitalPinToBitMask(pin);
    		} else {
    			*portClearRegister(pin) = digitalPinToBitMask(pin);
    		}
    	}
    }
    
    uint8_t digitalRead(uint8_t pin);
    static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused));
    static inline uint8_t digitalReadFast(uint8_t pin)
    {
    	if (__builtin_constant_p(pin)) {
    		if (pin == 0) {
    			return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0;
    		} else if (pin == 1) {
    			return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0;
    		} else if (pin == 2) {
    			return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0;
    		} else if (pin == 3) {
    			return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0;
    		} else if (pin == 4) {
    			return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0;
    		} else if (pin == 5) {
    			return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0;
    		} else if (pin == 6) {
    			return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0;
    		} else if (pin == 7) {
    			return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0;
    		} else if (pin == 8) {
    			return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0;
    		} else if (pin == 9) {
    			return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0;
    		} else if (pin == 10) {
    			return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0;
    		} else if (pin == 11) {
    			return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0;
    		} else if (pin == 12) {
    			return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0;
    		} else if (pin == 13) {
    			return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0;
    		} else if (pin == 14) {
    			return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0;
    		} else if (pin == 15) {
    			return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0;
    		} else if (pin == 16) {
    			return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0;
    		} else if (pin == 17) {
    			return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0;
    		} else if (pin == 18) {
    			return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0;
    		} else if (pin == 19) {
    			return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0;
    		} else if (pin == 20) {
    			return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0;
    		} else if (pin == 21) {
    			return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0;
    		} else if (pin == 22) {
    			return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0;
    		} else if (pin == 23) {
    			return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0;
    		} else if (pin == 24) {
    			return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0;
    		} else if (pin == 25) {
    			return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0;
    		} else if (pin == 26) {
    			return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0;
    		}
    		#if defined(CORE_PIN27_PINREG)
    		  else if (pin == 27) {
    			return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0;
    		} else if (pin == 28) {
    			return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0;
    		} else if (pin == 29) {
    			return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0;
    		} else if (pin == 30) {
    			return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0;
    		} else if (pin == 31) {
    			return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0;
    		} else if (pin == 32) {
    			return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;
    		} else if (pin == 33) {
    			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;
    		}
    		#endif
    		#if defined(CORE_PIN34_PINREG)
    		  else if (pin == 34) {
    			return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0;
    		} else if (pin == 35) {
    			return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0;
    		} else if (pin == 36) {
    			return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0;
    		} else if (pin == 37) {
    			return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0;
    		} else if (pin == 38) {
    			return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0;
    		} else if (pin == 39) {
    			return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0;
    		} else if (pin == 40) {
    			return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0;
    		} else if (pin == 41) {
    			return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0;
    		} else if (pin == 42) {
    			return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0;
    		} else if (pin == 43) {
    			return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0;
    		} else if (pin == 44) {
    			return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0;
    		} else if (pin == 45) {
    			return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0;
    		} else if (pin == 46) {
    			return (CORE_PIN46_PINREG & CORE_PIN46_BITMASK) ? 1 : 0;
    		} else if (pin == 47) {
    			return (CORE_PIN47_PINREG & CORE_PIN47_BITMASK) ? 1 : 0;
    		} else if (pin == 48) {
    			return (CORE_PIN48_PINREG & CORE_PIN48_BITMASK) ? 1 : 0;
    		} else if (pin == 49) {
    			return (CORE_PIN49_PINREG & CORE_PIN49_BITMASK) ? 1 : 0;
    		} else if (pin == 50) {
    			return (CORE_PIN50_PINREG & CORE_PIN50_BITMASK) ? 1 : 0;
    		} else if (pin == 51) {
    			return (CORE_PIN51_PINREG & CORE_PIN51_BITMASK) ? 1 : 0;
    		} else if (pin == 52) {
    			return (CORE_PIN52_PINREG & CORE_PIN52_BITMASK) ? 1 : 0;
    		} else if (pin == 53) {
    			return (CORE_PIN53_PINREG & CORE_PIN53_BITMASK) ? 1 : 0;
    		} else if (pin == 54) {
    			return (CORE_PIN54_PINREG & CORE_PIN54_BITMASK) ? 1 : 0;
    		} else if (pin == 55) {
    			return (CORE_PIN55_PINREG & CORE_PIN55_BITMASK) ? 1 : 0;
    		} else if (pin == 56) {
    			return (CORE_PIN56_PINREG & CORE_PIN56_BITMASK) ? 1 : 0;
    		} else if (pin == 57) {
    			return (CORE_PIN57_PINREG & CORE_PIN57_BITMASK) ? 1 : 0;
    		} else if (pin == 58) {
    			return (CORE_PIN58_PINREG & CORE_PIN58_BITMASK) ? 1 : 0;
    		} else if (pin == 59) {
    			return (CORE_PIN59_PINREG & CORE_PIN59_BITMASK) ? 1 : 0;
    		} else if (pin == 60) {
    			return (CORE_PIN60_PINREG & CORE_PIN60_BITMASK) ? 1 : 0;
    		} else if (pin == 61) {
    			return (CORE_PIN61_PINREG & CORE_PIN61_BITMASK) ? 1 : 0;
    		} else if (pin == 62) {
    			return (CORE_PIN62_PINREG & CORE_PIN62_BITMASK) ? 1 : 0;
    		} else if (pin == 63) {
    			return (CORE_PIN63_PINREG & CORE_PIN63_BITMASK) ? 1 : 0;
    		} else if (pin == PTA6) {
    			return (CORE_PTA6_PINREG & CORE_PTA6_BITMASK) ? 1 : 0;
    		} else if (pin == PTA7) {
    			return (CORE_PTA7_PINREG & CORE_PTA7_BITMASK) ? 1 : 0;
    		} else if (pin == PTA8) {
    			return (CORE_PTA8_PINREG & CORE_PTA8_BITMASK) ? 1 : 0;
    		}
    		#endif
    		  else {
    			return 0;
    		}
    	} else {
    		#if defined(KINETISK)
    		return *portInputRegister(pin);
    		#else
    		return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0;
    		#endif
    	}
    }
    
    
    void pinMode(uint8_t pin, uint8_t mode);
    void init_pins(void);
    void analogWrite(uint8_t pin, int val);
    uint32_t analogWriteRes(uint32_t bits);
    static inline uint32_t analogWriteResolution(uint32_t bits) { return analogWriteRes(bits); }
    void analogWriteFrequency(uint8_t pin, float frequency);
    void analogWriteDAC0(int val);
    void analogWriteDAC1(int val);
    #ifdef __cplusplus
    void attachInterruptVector(IRQ_NUMBER_t irq, void (*function)(void));
    #else
    void attachInterruptVector(enum IRQ_NUMBER_t irq, void (*function)(void));
    #endif
    void attachInterrupt(uint8_t pin, void (*function)(void), int mode);
    void detachInterrupt(uint8_t pin);
    void _init_Teensyduino_internal_(void);
    
    int analogRead(uint8_t pin);
    void analogReference(uint8_t type);
    void analogReadRes(unsigned int bits);
    static inline void analogReadResolution(unsigned int bits) { analogReadRes(bits); }
    void analogReadAveraging(unsigned int num);
    void analog_init(void);
    
    
    
    #define DEFAULT         0
    #define INTERNAL        2
    #define INTERNAL1V2     2
    #define INTERNAL1V1     2
    #define EXTERNAL        0
    
    
    
    
    int touchRead(uint8_t pin);
    
    
    static inline void shiftOut(uint8_t, uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));
    extern void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) __attribute__((noinline));
    extern void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));
    extern void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));
    
    static inline void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)
    {
            if (__builtin_constant_p(bitOrder)) {
                    if (bitOrder == LSBFIRST) {
                            shiftOut_lsbFirst(dataPin, clockPin, value);
                    } else {
                            shiftOut_msbFirst(dataPin, clockPin, value);
                    }
            } else {
                    _shiftOut(dataPin, clockPin, bitOrder, value);
            }
    }
    
    static inline uint8_t shiftIn(uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));
    extern uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) __attribute__((noinline));
    extern uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));
    extern uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));
    
    static inline uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)
    {
            if (__builtin_constant_p(bitOrder)) {
                    if (bitOrder == LSBFIRST) {
                            return shiftIn_lsbFirst(dataPin, clockPin);
                    } else {
                            return shiftIn_msbFirst(dataPin, clockPin);
                    }
            } else {
                    return _shiftIn(dataPin, clockPin, bitOrder);
            }
    }
    
    void _reboot_Teensyduino_(void) __attribute__((noreturn));
    void _restart_Teensyduino_(void) __attribute__((noreturn));
    
    void yield(void);
    
    void delay(uint32_t msec);
    
    extern volatile uint32_t systick_millis_count;
    
    static inline uint32_t millis(void) __attribute__((always_inline, unused));
    static inline uint32_t millis(void)
    {
    	// Reading a volatile variable to another volatile
    	// seems redundant, but isn't for some cases.
    	// Eventually this should probably be replaced by a
    	// proper memory barrier or other technique.  Please
    	// do not remove this "redundant" code without
    	// carefully verifying the case mentioned here:
    	//
    	// https://forum.pjrc.com/threads/17469-millis%28%29-on-teensy-3?p=104924&viewfull=1#post104924
    	//
    	volatile uint32_t ret = systick_millis_count; // single aligned 32 bit is atomic
    	return ret;
    }
    
    uint32_t micros(void);
    
    static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));
    static inline void delayMicroseconds(uint32_t usec)
    {
    #if F_CPU == 240000000
    	uint32_t n = usec * 80;
    #elif F_CPU == 216000000
    	uint32_t n = usec * 72;
    #elif F_CPU == 192000000
    	uint32_t n = usec * 64;
    #elif F_CPU == 180000000
    	uint32_t n = usec * 60;
    #elif F_CPU == 168000000
    	uint32_t n = usec * 56;
    #elif F_CPU == 144000000
    	uint32_t n = usec * 48;
    #elif F_CPU == 120000000
    	uint32_t n = usec * 40;
    #elif F_CPU == 96000000
    	uint32_t n = usec << 5;
    #elif F_CPU == 72000000
    	uint32_t n = usec * 24;
    #elif F_CPU == 48000000
    	uint32_t n = usec << 4;
    #elif F_CPU == 24000000
    	uint32_t n = usec << 3;
    #elif F_CPU == 16000000
    	uint32_t n = usec << 2;
    #elif F_CPU == 8000000
    	uint32_t n = usec << 1;
    #elif F_CPU == 4000000
    	uint32_t n = usec;
    #elif F_CPU == 2000000
    	uint32_t n = usec >> 1;
    #endif
        // changed because a delay of 1 micro Sec @ 2MHz will be 0
    	if (n == 0) return;
    	__asm__ volatile(
    		"L_%=_delayMicroseconds:"		"\n\t"
    #if F_CPU < 24000000
    		"nop"					"\n\t"
    #endif
    #ifdef KINETISL
    		"sub    %0, #1"				"\n\t"
    #else
    		"subs   %0, #1"				"\n\t"
    #endif
    		"bne    L_%=_delayMicroseconds"		"\n"
    		: "+r" (n) :
    	);
    }
    
    #ifdef __cplusplus
    }
    #endif
    
    
    
    
    
    
    
    
    #ifdef __cplusplus
    extern "C" {
    #endif
    unsigned long rtc_get(void);
    void rtc_set(unsigned long t);
    void rtc_compensate(int adjust);
    #ifdef __cplusplus
    }
    class teensy3_clock_class
    {
    public:
    	static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); }
    	static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); }
    	static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); }
    };
    extern teensy3_clock_class Teensy3Clock;
    #endif
    
    
    
    
    #endif
    Last edited by finchamp; 10-26-2018 at 10:47 PM.

  4. #29
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    You may remove PTE6 from your list of free pins, as it is used in T3.6 to enable USB limiter TPD3S014.
    on the other side PTE0-5, while used in SD card, they are still accessible using an adaptor, they are also used for SPI1 and got already numbers by KurtE.

  5. #30
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by WMXZ View Post
    ...
    on the other side PTE0-5, while used in SD card, they are still accessible using an adaptor, they are also used for SPI1 and got already numbers by KurtE.
    See post #4 for the numbers of those pins - perfectly usable when SD not in use.

  6. #31
    Senior Member+ KurtE's Avatar
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    Quote Originally Posted by WMXZ View Post
    You may remove PTE6 from your list of free pins, as it is used in T3.6 to enable USB limiter TPD3S014.
    on the other side PTE0-5, while used in SD card, they are still accessible using an adaptor, they are also used for SPI1 and got already numbers by KurtE.
    Yes they are fully usable for GPIO pins as well as SPI1. For awhile during testing, I had an ILI9341 display fully hooked up to one of the Adapters I made, so when I wanted to run a test on these boards that I wished to display something, you just had to plug in the SD adapter and away you went.

    Note: these pins also have alternate pins for I2C1 as well as alternate pins for Serial2(UART1) and Serial4(UART3)...

    Here is extract from my Excel document... Sorry that all of the columns probably don't align properly...

    Code:
    58	PTE0	ADC1_SE4a	ADC1_SE4a	PTE0		SPI1_PCS1	UART1_TX	SDHC1_D1	TRACE_CLKOUT	I2C1_SDA	RTC_CLKOUT
    59	PTE1	ADC1_SE5a	ADC1_SE5a	PTE1/LLWU_P0	SPI1_SOUT	UART1_RX	SDHC0_D0	TRACE_D3	I2C1_SCL	SPI1_SIN
    60	PTE2	PTE2/LLWU_P1	ADC1_SE6a	PTE2/LLWU_P1	SPI1_SCK	UART1_CTS_b	SDHC0_DCLK	TRACE_D2		
    61	PTE3	ADC1_SE7a	ADC1_SE7a	PTE3		SPI1_SIN	UART1_RTS_b	SDHC0_CMD	TRACE_D1			SPI1_SOUT
    62	PTE4	DISABLED			PTE4/LLWU_P2	SPI1_PCS0	UART3_TX	SDHC0_D3	TRACE_D0		
    63	PTE5	DISABLED			PTE5		SPI1_PCS2	UART3_RX	SDHC0_D2		FTM3_CH0

  7. #32
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    Thanks folks. I was aware that the SD bus pins are usable on standalones, but I copied from brtaylor's list above, and I haven't worked down to PTE0-4 yet. Would love for somebody to confirm or deny that PTA 7 and 8 are working before I continue.

    I will remove PTA6, thanks WMXZ.

  8. #33
    Senior Member brtaylor's Avatar
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    Quote Originally Posted by finchamp View Post
    Thanks folks. I was aware that the SD bus pins are usable on standalones, but I copied from brtaylor's list above, and I haven't worked down to PTE0-4 yet. Would love for somebody to confirm or deny that PTA 7 and 8 are working before I continue.

    I will remove PTA6, thanks WMXZ.
    PTA6 is weird - it's not available on Teensy 3.6, but may be available on other boards that aren't using a TPD3S014.

  9. #34
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    Quote Originally Posted by brtaylor View Post
    PTA6 is weird - it's not available on Teensy 3.6, but may be available on other boards that aren't using a TPD3S014.
    Yes, but then custom Teensy cannot be non-interfering with T3.x.

  10. #35
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by brtaylor View Post
    PTA6 is weird - it's not available on Teensy 3.6, but may be available on other boards that aren't using a TPD3S014.
    PTE6, not PTA6, is the signal connected to enable the TPD3S014 USB host power switch.


  11. #36
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    Quote Originally Posted by finchamp View Post
    Would love for somebody to confirm or deny that PTA 7 and 8 are working before I continue.
    Should be a great job for defragster's custom design when the first prototypes are available ;-)

  12. #37
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    Quote Originally Posted by finchamp View Post
    Okay, this is VERY preliminary, and essentially untested. However, it DOES compile. I'm just hoping that this works the way it looks to, as I haven't spent as much time in the datasheet and libraries as most of you. This code belongs to Paul, so thanks again.

    You can refer to the extra pins numerically (PTA6 is "pin" 70; see file), or by their proper name (PTA6). I also added definitions to allow referring to Teensy-defined pins by their proper names. I have only added conditions for PTA6-8 for testing purposes, and only digital. Back up your core_pins.h, and replace it with the following (ONLY supports MK66!). I don't have my hardware yet, so somebody test this!
    Any news here?
    Unfortunately I could not test this yet due to missing hardware...

    Two things about this approach:
    1. There is a numbering failure around PTD10
    2. As far as I know and according to analog.c "Pins" 70 and 71 are used for internal connections to the ADC which can read the internal temperature sensor and obviously Vref - so we should start with Pin 72. Is this correct? Are there any more Pins already defined?!

    I created a card like the original Teensy ones for this extended pin numbering, using the LQFP144 package.
    The light grey boxes are extended pins, the red writing are suggested pin numbers/names according to finchamps list with the mentioned two adjustments.
    Please let me know if there are any mistakes or make further suggestions...

    Click image for larger version. 

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  13. #38
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    Found a few bugs
    - changed color to dark green for 72/PTA18
    - added another analog input 28/0_DMO and changed numbering
    - added Serial6 at 137/PTD8 and 138/PTD9
    - left out numbering for PTE6
    - chose a darker grey for PTA4 and PTE6

    As an addition for PTA4 (and PTE6), my suggestion is to leave this pin completely out of the extended numbering to avoid any problems and maintain compatibility to standard T3.6

    Click image for larger version. 

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  14. #39
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    Michael, that's really smashing work! Thanks a lot! It will indeed come in handy.

    Good catch on the pin numbering, I tried to give a bit of buffer, but not enough, obviously. I will rework my pin definitions accordingly when I get to testing.

    I haven't made any progress on actual testing, as I'm waiting on my hardware as well. Shouldn't be too long, though.

  15. #40
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by MichaelB View Post
    Should be a great job for defragster's custom design when the first prototypes are available ;-)
    Just seeing this - … wasn't working on "defragster's custom design"

    Wondering if these new/extended numbers might want a big cusp to start at 128 to leave space to future PJRC product pins? And 'if ( 0x80 & pin#)' Might allow a few spots in code to easily identify these extended pin functions as well.

    [ yikes - that was post #7,000 ]

  16. #41
    Senior Member+ Theremingenieur's Avatar
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    Quote Originally Posted by defragster View Post
    [ yikes - that was post #7,000 ]
    How do you say in English - tattletale?

  17. #42
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by Theremingenieur View Post
    How do you say in English - tattletale?
    Perhaps 'showoff' or braggart? tattletale is when you tell on someone else … something they didn't want known.

    … was just to be a casual note though since the next post increments on all posts.

  18. #43
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    Quote Originally Posted by defragster View Post
    Just seeing this - … wasn't working on "defragster's custom design"
    Sorry about that, mixed something up here - I meant brtaylors Teensy 3.6 "Pro".

    Quote Originally Posted by defragster View Post
    Wondering if these new/extended numbers might want a big cusp to start at 128 to leave space to future PJRC product pins? And 'if ( 0x80 & pin#)' Might allow a few spots in code to easily identify these extended pin functions as well.
    Good point.
    Suggestion for the pure analog ones?

  19. #44
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    I'm finally getting back to this. I have hardware on hand that gives me access to the additional IO, and have started some basic testing. FYI, I have reworked my definitions to follow MichaelB's graphic, and am considering that the "official" standard for this project. Updated code below.

    Unfortunately, straight away I'm finding that pinMode(OUTPUT) freezes the microcontroller when called for any of the new pins. If anyone wants to dig through the core and see where I mucked up, feel free.

    core_pins.h
    Code:
    /* Extended pin definitions for standalone MK66 projects compatible with the Teensy 3.6 toolchain.
     * Based on Teensyduino Core Library - core_pins.h, V1.44
     * Copyright (c) 2017 PJRC.COM, LLC.
     
     * No affiliation with PJRC, no warranty or support expressed or implied.
     * https://forum.pjrc.com/threads/54114-Extended-Pin-Numbering
    */
    
    #ifndef _core_pins_h_
    #define _core_pins_h_
    
    #include "kinetis.h"
    #include "pins_arduino.h"
    
    #define HIGH		1
    #define LOW		0
    #define INPUT		0
    #define OUTPUT		1
    #define INPUT_PULLUP	2
    #define INPUT_PULLDOWN   3
    #define OUTPUT_OPENDRAIN 4
    #define INPUT_DISABLE   5
    #define LSBFIRST	0
    #define MSBFIRST	1
    #define _BV(n)		(1<<(n))
    #define CHANGE		4
    #define FALLING		2
    #define RISING		3
    
    
    #if defined(__MK66FX1M0__)
    #define CORE_NUM_TOTAL_PINS     97	// up from 64; double-check that these are all available
    #define CORE_NUM_DIGITAL        97	// up from 64; double-check that these are all available
    #define CORE_NUM_INTERRUPT      64	// need to research interrupt capabilities
    #define CORE_NUM_ANALOG         36  // double-check that these are all available
    #define CORE_NUM_PWM            22	// haven't looked at this
    #else 
    	#error "Incorrect processor selected! This library only compatible with NXP MK66/Teensy 3.6!"  // Guarantees that this library extension is not used with any non-target processors
    #endif
    
    // These MAX_PIN_PORTx values have the highest Kinetis pin index
    // that is used for a given port.
    #define CORE_MAX_PIN_PORTA        29
    #define CORE_MAX_PIN_PORTB        23
    #define CORE_MAX_PIN_PORTC        19	// Up from 11
    #define CORE_MAX_PIN_PORTD        15
    #define CORE_MAX_PIN_PORTE        28	// Up from 26
    
    //---- Begin new definitions
    // DO NOT DEFINE PTA0-4
    // 64-69 already defined in pins_arduino.h
    #define PTA5			25
    #define PTA6			72 // new
    #define PTA7			73 // new
    #define PTA8			74 // new
    #define PTA9			75 // new
    #define PTA10			76 // new
    #define PTA11			77 // new
    #define PTA12			3
    #define PTA13			4
    #define PTA14			26
    #define PTA15			27
    #define PTA16			28
    #define PTA17			39
    #define PTA24			78 // new
    #define PTA25			79 // new
    #define PTA26			42
    #define PTA27			80 // new
    #define PTA28			40
    #define PTA29			41
    #define PTB0			16
    #define PTB1			17
    #define PTB2			19
    #define PTB3			18
    #define PTB4			49
    #define PTB5			50
    #define PTB6			81 // new
    #define PTB7			82 // new
    #define PTB8			83 // new
    #define PTB9			84 // new
    #define PTB10			31
    #define PTB11			32
    #define PTB16			0
    #define PTB17			1
    #define PTB18			29
    #define PTB19			30
    #define PTB20			43
    #define PTB21			46
    #define PTB22			44
    #define PTB23			45
    #define PTC0			15
    #define PTC1			22
    #define PTC2			23
    #define PTC3			9
    #define PTC4			10
    #define PTC5			13
    #define PTC6			11
    #define PTC7			12
    #define PTC8			35
    #define PTC9			36
    #define PTC10			37
    #define PTC11			38
    #define PTC12			85 // new
    #define PTC13			86 // new
    #define PTC14			87 // new
    #define PTC15			88 // new
    #define PTC16			89 // new
    #define PTC17			90 // new
    #define PTC18			91 // new
    #define PTC19			92 // new
    #define PTD0			2
    #define PTD1			14
    #define PTD2			7
    #define PTD3			8
    #define PTD4			6
    #define PTD5			20
    #define PTD6			21
    #define PTD7			5
    #define PTD8			47
    #define PTD9			48
    #define PTD10			93 // new
    #define PTD11			55
    #define PTD12			53
    #define PTD13			52
    #define PTD14			51
    #define PTD15			54
    //#define PTE0			N/A Built In SD
    //#define PTE1			N/A Built In SD
    //#define PTE2			N/A Built In SD
    //#define PTE3			N/A Built In SD
    //#define PTE4			N/A Built In SD
    //#define PTE5			N/A Built In SD
    //#define PTE6			000  DO NOT DEFINE
    #define PTE7			94 // new
    #define PTE8			95 // new
    #define PTE9			96 // new
    #define PTE10			56
    #define PTE11			57
    #define PTE12			97 // new
    #define PTE24			33
    #define PTE25			34
    #define PTE26			24
    #define PTE27			98 // new
    #define PTE28			99 // new
    
    
    // PTA6
    #define CORE_PIN72_BIT		6
    #define CORE_PIN72_BITMASK	(1<<(CORE_PIN72_BIT))
    #define CORE_PIN72_PORTREG	GPIOA_PDOR
    #define CORE_PIN72_PORTSET	GPIOA_PSOR
    #define CORE_PIN72_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN72_DDRREG	GPIOA_PDDR
    #define CORE_PIN72_PINREG	GPIOA_PDIR
    #define CORE_PIN72_CONFIG	PORTA_PCR6
    #define CORE_INT72_PIN		72
    #define CORE_FTM3_CH0_PIN	72
    
    // PTA7
    #define CORE_PIN73_BIT		7
    #define CORE_PIN73_BITMASK	(1<<(CORE_PIN73_BIT))
    #define CORE_PIN73_PORTREG	GPIOA_PDOR
    #define CORE_PIN73_PORTSET	GPIOA_PSOR
    #define CORE_PIN73_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN73_DDRREG	GPIOA_PDDR
    #define CORE_PIN73_PINREG	GPIOA_PDIR
    #define CORE_PIN73_CONFIG	PORTA_PCR7
    #define CORE_INT73_PIN		73
    #define CORE_FTM4_CH0_PIN	73
    
    // PTA8
    #define CORE_PIN74_BIT		8
    #define CORE_PIN74_BITMASK	(1<<(CORE_PIN74_BIT))
    #define CORE_PIN74_PORTREG	GPIOA_PDOR
    #define CORE_PIN74_PORTSET	GPIOA_PSOR
    #define CORE_PIN74_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN74_DDRREG	GPIOA_PDDR
    #define CORE_PIN74_PINREG	GPIOA_PDIR
    #define CORE_PIN74_CONFIG	PORTA_PCR8
    #define CORE_INT74_PIN		74
    #define CORE_FTM0_CH1_PIN	74
    
    
    //---- End new definitions
    
    
    #define CORE_PIN0_BIT		16
    #define CORE_PIN1_BIT		17
    #define CORE_PIN2_BIT		0
    #define CORE_PIN3_BIT		12
    #define CORE_PIN4_BIT		13
    #define CORE_PIN5_BIT		7
    #define CORE_PIN6_BIT		4
    #define CORE_PIN7_BIT		2
    #define CORE_PIN8_BIT		3
    #define CORE_PIN9_BIT		3
    #define CORE_PIN10_BIT		4
    #define CORE_PIN11_BIT		6
    #define CORE_PIN12_BIT		7
    #define CORE_PIN13_BIT		5
    #define CORE_PIN14_BIT		1
    #define CORE_PIN15_BIT		0
    #define CORE_PIN16_BIT		0
    #define CORE_PIN17_BIT		1
    #define CORE_PIN18_BIT		3
    #define CORE_PIN19_BIT		2
    #define CORE_PIN20_BIT		5
    #define CORE_PIN21_BIT		6
    #define CORE_PIN22_BIT		1
    #define CORE_PIN23_BIT		2
    #define CORE_PIN24_BIT		26
    #define CORE_PIN25_BIT		5
    #define CORE_PIN26_BIT		14
    #define CORE_PIN27_BIT		15
    #define CORE_PIN28_BIT		16
    #define CORE_PIN29_BIT		18
    #define CORE_PIN30_BIT		19
    #define CORE_PIN31_BIT		10
    #define CORE_PIN32_BIT		11
    #define CORE_PIN33_BIT		24
    #define CORE_PIN34_BIT		25
    #define CORE_PIN35_BIT		8
    #define CORE_PIN36_BIT		9
    #define CORE_PIN37_BIT		10
    #define CORE_PIN38_BIT		11
    #define CORE_PIN39_BIT		17
    #define CORE_PIN40_BIT		28
    #define CORE_PIN41_BIT		29
    #define CORE_PIN42_BIT		26
    #define CORE_PIN43_BIT		20
    #define CORE_PIN44_BIT		22
    #define CORE_PIN45_BIT		23
    #define CORE_PIN46_BIT		21
    #define CORE_PIN47_BIT		8
    #define CORE_PIN48_BIT		9
    #define CORE_PIN49_BIT		4
    #define CORE_PIN50_BIT		5
    #define CORE_PIN51_BIT		14
    #define CORE_PIN52_BIT		13
    #define CORE_PIN53_BIT		12
    #define CORE_PIN54_BIT		15
    #define CORE_PIN55_BIT		11
    #define CORE_PIN56_BIT		10
    #define CORE_PIN57_BIT		11
    #define CORE_PIN58_BIT		0
    #define CORE_PIN59_BIT		1
    #define CORE_PIN60_BIT		2
    #define CORE_PIN61_BIT		3
    #define CORE_PIN62_BIT		4
    #define CORE_PIN63_BIT		5
    
    #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))
    #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))
    #define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))
    #define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))
    #define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))
    #define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))
    #define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))
    #define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))
    #define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))
    #define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))
    #define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))
    #define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))
    #define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))
    #define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))
    #define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))
    #define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))
    #define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))
    #define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))
    #define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))
    #define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))
    #define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))
    #define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))
    #define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))
    #define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))
    #define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))
    #define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))
    #define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))
    #define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))
    #define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))
    #define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))
    #define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))
    #define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))
    #define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))
    #define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))
    #define CORE_PIN34_BITMASK	(1<<(CORE_PIN34_BIT))
    #define CORE_PIN35_BITMASK	(1<<(CORE_PIN35_BIT))
    #define CORE_PIN36_BITMASK	(1<<(CORE_PIN36_BIT))
    #define CORE_PIN37_BITMASK	(1<<(CORE_PIN37_BIT))
    #define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))
    #define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))
    #define CORE_PIN40_BITMASK	(1<<(CORE_PIN40_BIT))
    #define CORE_PIN41_BITMASK	(1<<(CORE_PIN41_BIT))
    #define CORE_PIN42_BITMASK	(1<<(CORE_PIN42_BIT))
    #define CORE_PIN43_BITMASK	(1<<(CORE_PIN43_BIT))
    #define CORE_PIN44_BITMASK	(1<<(CORE_PIN44_BIT))
    #define CORE_PIN45_BITMASK	(1<<(CORE_PIN45_BIT))
    #define CORE_PIN46_BITMASK	(1<<(CORE_PIN46_BIT))
    #define CORE_PIN47_BITMASK	(1<<(CORE_PIN47_BIT))
    #define CORE_PIN48_BITMASK	(1<<(CORE_PIN48_BIT))
    #define CORE_PIN49_BITMASK	(1<<(CORE_PIN49_BIT))
    #define CORE_PIN50_BITMASK	(1<<(CORE_PIN50_BIT))
    #define CORE_PIN51_BITMASK	(1<<(CORE_PIN51_BIT))
    #define CORE_PIN52_BITMASK	(1<<(CORE_PIN52_BIT))
    #define CORE_PIN53_BITMASK	(1<<(CORE_PIN53_BIT))
    #define CORE_PIN54_BITMASK	(1<<(CORE_PIN54_BIT))
    #define CORE_PIN55_BITMASK	(1<<(CORE_PIN55_BIT))
    #define CORE_PIN56_BITMASK	(1<<(CORE_PIN56_BIT))
    #define CORE_PIN57_BITMASK	(1<<(CORE_PIN57_BIT))
    #define CORE_PIN58_BITMASK	(1<<(CORE_PIN58_BIT))
    #define CORE_PIN59_BITMASK	(1<<(CORE_PIN59_BIT))
    #define CORE_PIN60_BITMASK	(1<<(CORE_PIN60_BIT))
    #define CORE_PIN61_BITMASK	(1<<(CORE_PIN61_BIT))
    #define CORE_PIN62_BITMASK	(1<<(CORE_PIN62_BIT))
    #define CORE_PIN63_BITMASK	(1<<(CORE_PIN63_BIT))
    
    
    #define CORE_PIN0_PORTREG	GPIOB_PDOR
    #define CORE_PIN1_PORTREG	GPIOB_PDOR
    #define CORE_PIN2_PORTREG	GPIOD_PDOR
    #define CORE_PIN3_PORTREG	GPIOA_PDOR
    #define CORE_PIN4_PORTREG	GPIOA_PDOR
    #define CORE_PIN5_PORTREG	GPIOD_PDOR
    #define CORE_PIN6_PORTREG	GPIOD_PDOR
    #define CORE_PIN7_PORTREG	GPIOD_PDOR
    #define CORE_PIN8_PORTREG	GPIOD_PDOR
    #define CORE_PIN9_PORTREG	GPIOC_PDOR
    #define CORE_PIN10_PORTREG	GPIOC_PDOR
    #define CORE_PIN11_PORTREG	GPIOC_PDOR
    #define CORE_PIN12_PORTREG	GPIOC_PDOR
    #define CORE_PIN13_PORTREG	GPIOC_PDOR
    #define CORE_PIN14_PORTREG	GPIOD_PDOR
    #define CORE_PIN15_PORTREG	GPIOC_PDOR
    #define CORE_PIN16_PORTREG	GPIOB_PDOR
    #define CORE_PIN17_PORTREG	GPIOB_PDOR
    #define CORE_PIN18_PORTREG	GPIOB_PDOR
    #define CORE_PIN19_PORTREG	GPIOB_PDOR
    #define CORE_PIN20_PORTREG	GPIOD_PDOR
    #define CORE_PIN21_PORTREG	GPIOD_PDOR
    #define CORE_PIN22_PORTREG	GPIOC_PDOR
    #define CORE_PIN23_PORTREG	GPIOC_PDOR
    #define CORE_PIN24_PORTREG	GPIOE_PDOR
    #define CORE_PIN25_PORTREG	GPIOA_PDOR
    #define CORE_PIN26_PORTREG	GPIOA_PDOR
    #define CORE_PIN27_PORTREG	GPIOA_PDOR
    #define CORE_PIN28_PORTREG	GPIOA_PDOR
    #define CORE_PIN29_PORTREG	GPIOB_PDOR
    #define CORE_PIN30_PORTREG	GPIOB_PDOR
    #define CORE_PIN31_PORTREG	GPIOB_PDOR
    #define CORE_PIN32_PORTREG	GPIOB_PDOR
    #define CORE_PIN33_PORTREG	GPIOE_PDOR
    #define CORE_PIN34_PORTREG	GPIOE_PDOR
    #define CORE_PIN35_PORTREG	GPIOC_PDOR
    #define CORE_PIN36_PORTREG	GPIOC_PDOR
    #define CORE_PIN37_PORTREG	GPIOC_PDOR
    #define CORE_PIN38_PORTREG	GPIOC_PDOR
    #define CORE_PIN39_PORTREG	GPIOA_PDOR
    #define CORE_PIN40_PORTREG	GPIOA_PDOR
    #define CORE_PIN41_PORTREG	GPIOA_PDOR
    #define CORE_PIN42_PORTREG	GPIOA_PDOR
    #define CORE_PIN43_PORTREG	GPIOB_PDOR
    #define CORE_PIN44_PORTREG	GPIOB_PDOR
    #define CORE_PIN45_PORTREG	GPIOB_PDOR
    #define CORE_PIN46_PORTREG	GPIOB_PDOR
    #define CORE_PIN47_PORTREG	GPIOD_PDOR
    #define CORE_PIN48_PORTREG	GPIOD_PDOR
    #define CORE_PIN49_PORTREG	GPIOB_PDOR
    #define CORE_PIN50_PORTREG	GPIOB_PDOR
    #define CORE_PIN51_PORTREG	GPIOD_PDOR
    #define CORE_PIN52_PORTREG	GPIOD_PDOR
    #define CORE_PIN53_PORTREG	GPIOD_PDOR
    #define CORE_PIN54_PORTREG	GPIOD_PDOR
    #define CORE_PIN55_PORTREG	GPIOD_PDOR
    #define CORE_PIN56_PORTREG	GPIOE_PDOR
    #define CORE_PIN57_PORTREG	GPIOE_PDOR
    #define CORE_PIN58_PORTREG	GPIOE_PDOR
    #define CORE_PIN59_PORTREG	GPIOE_PDOR
    #define CORE_PIN60_PORTREG	GPIOE_PDOR
    #define CORE_PIN61_PORTREG	GPIOE_PDOR
    #define CORE_PIN62_PORTREG	GPIOE_PDOR
    #define CORE_PIN63_PORTREG	GPIOE_PDOR
    
    #define CORE_PIN0_PORTSET	GPIOB_PSOR
    #define CORE_PIN1_PORTSET	GPIOB_PSOR
    #define CORE_PIN2_PORTSET	GPIOD_PSOR
    #define CORE_PIN3_PORTSET	GPIOA_PSOR
    #define CORE_PIN4_PORTSET	GPIOA_PSOR
    #define CORE_PIN5_PORTSET	GPIOD_PSOR
    #define CORE_PIN6_PORTSET	GPIOD_PSOR
    #define CORE_PIN7_PORTSET	GPIOD_PSOR
    #define CORE_PIN8_PORTSET	GPIOD_PSOR
    #define CORE_PIN9_PORTSET	GPIOC_PSOR
    #define CORE_PIN10_PORTSET	GPIOC_PSOR
    #define CORE_PIN11_PORTSET	GPIOC_PSOR
    #define CORE_PIN12_PORTSET	GPIOC_PSOR
    #define CORE_PIN13_PORTSET	GPIOC_PSOR
    #define CORE_PIN14_PORTSET	GPIOD_PSOR
    #define CORE_PIN15_PORTSET	GPIOC_PSOR
    #define CORE_PIN16_PORTSET	GPIOB_PSOR
    #define CORE_PIN17_PORTSET	GPIOB_PSOR
    #define CORE_PIN18_PORTSET	GPIOB_PSOR
    #define CORE_PIN19_PORTSET	GPIOB_PSOR
    #define CORE_PIN20_PORTSET	GPIOD_PSOR
    #define CORE_PIN21_PORTSET	GPIOD_PSOR
    #define CORE_PIN22_PORTSET	GPIOC_PSOR
    #define CORE_PIN23_PORTSET	GPIOC_PSOR
    #define CORE_PIN24_PORTSET	GPIOE_PSOR
    #define CORE_PIN25_PORTSET	GPIOA_PSOR
    #define CORE_PIN26_PORTSET	GPIOA_PSOR
    #define CORE_PIN27_PORTSET	GPIOA_PSOR
    #define CORE_PIN28_PORTSET	GPIOA_PSOR
    #define CORE_PIN29_PORTSET	GPIOB_PSOR
    #define CORE_PIN30_PORTSET	GPIOB_PSOR
    #define CORE_PIN31_PORTSET	GPIOB_PSOR
    #define CORE_PIN32_PORTSET	GPIOB_PSOR
    #define CORE_PIN33_PORTSET	GPIOE_PSOR
    #define CORE_PIN34_PORTSET	GPIOE_PSOR
    #define CORE_PIN35_PORTSET	GPIOC_PSOR
    #define CORE_PIN36_PORTSET	GPIOC_PSOR
    #define CORE_PIN37_PORTSET	GPIOC_PSOR
    #define CORE_PIN38_PORTSET	GPIOC_PSOR
    #define CORE_PIN39_PORTSET	GPIOA_PSOR
    #define CORE_PIN40_PORTSET	GPIOA_PSOR
    #define CORE_PIN41_PORTSET	GPIOA_PSOR
    #define CORE_PIN42_PORTSET	GPIOA_PSOR
    #define CORE_PIN43_PORTSET	GPIOB_PSOR
    #define CORE_PIN44_PORTSET	GPIOB_PSOR
    #define CORE_PIN45_PORTSET	GPIOB_PSOR
    #define CORE_PIN46_PORTSET	GPIOB_PSOR
    #define CORE_PIN47_PORTSET	GPIOD_PSOR
    #define CORE_PIN48_PORTSET	GPIOD_PSOR
    #define CORE_PIN49_PORTSET	GPIOB_PSOR
    #define CORE_PIN50_PORTSET	GPIOB_PSOR
    #define CORE_PIN51_PORTSET	GPIOD_PSOR
    #define CORE_PIN52_PORTSET	GPIOD_PSOR
    #define CORE_PIN53_PORTSET	GPIOD_PSOR
    #define CORE_PIN54_PORTSET	GPIOD_PSOR
    #define CORE_PIN55_PORTSET	GPIOD_PSOR
    #define CORE_PIN56_PORTSET	GPIOE_PSOR
    #define CORE_PIN57_PORTSET	GPIOE_PSOR
    #define CORE_PIN58_PORTSET	GPIOE_PSOR
    #define CORE_PIN59_PORTSET	GPIOE_PSOR
    #define CORE_PIN60_PORTSET	GPIOE_PSOR
    #define CORE_PIN61_PORTSET	GPIOE_PSOR
    #define CORE_PIN62_PORTSET	GPIOE_PSOR
    #define CORE_PIN63_PORTSET	GPIOE_PSOR
    
    #define CORE_PIN0_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN1_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN2_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN3_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN4_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN5_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN6_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN7_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN8_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN9_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN10_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN11_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN12_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN13_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN14_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN15_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN16_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN17_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN18_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN19_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN20_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN21_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN22_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN23_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN24_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN25_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN26_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN27_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN28_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN29_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN30_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN31_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN32_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN33_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN34_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN35_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN36_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN37_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN38_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN39_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN40_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN41_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN42_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN43_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN44_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN45_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN46_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN47_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN48_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN49_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN50_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN51_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN52_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN53_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN54_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN55_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN56_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN57_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN58_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN59_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN60_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN61_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN62_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN63_PORTCLEAR	GPIOE_PCOR
    
    #define CORE_PIN0_DDRREG	GPIOB_PDDR
    #define CORE_PIN1_DDRREG	GPIOB_PDDR
    #define CORE_PIN2_DDRREG	GPIOD_PDDR
    #define CORE_PIN3_DDRREG	GPIOA_PDDR
    #define CORE_PIN4_DDRREG	GPIOA_PDDR
    #define CORE_PIN5_DDRREG	GPIOD_PDDR
    #define CORE_PIN6_DDRREG	GPIOD_PDDR
    #define CORE_PIN7_DDRREG	GPIOD_PDDR
    #define CORE_PIN8_DDRREG	GPIOD_PDDR
    #define CORE_PIN9_DDRREG	GPIOC_PDDR
    #define CORE_PIN10_DDRREG	GPIOC_PDDR
    #define CORE_PIN11_DDRREG	GPIOC_PDDR
    #define CORE_PIN12_DDRREG	GPIOC_PDDR
    #define CORE_PIN13_DDRREG	GPIOC_PDDR
    #define CORE_PIN14_DDRREG	GPIOD_PDDR
    #define CORE_PIN15_DDRREG	GPIOC_PDDR
    #define CORE_PIN16_DDRREG	GPIOB_PDDR
    #define CORE_PIN17_DDRREG	GPIOB_PDDR
    #define CORE_PIN18_DDRREG	GPIOB_PDDR
    #define CORE_PIN19_DDRREG	GPIOB_PDDR
    #define CORE_PIN20_DDRREG	GPIOD_PDDR
    #define CORE_PIN21_DDRREG	GPIOD_PDDR
    #define CORE_PIN22_DDRREG	GPIOC_PDDR
    #define CORE_PIN23_DDRREG	GPIOC_PDDR
    #define CORE_PIN24_DDRREG	GPIOE_PDDR
    #define CORE_PIN25_DDRREG	GPIOA_PDDR
    #define CORE_PIN26_DDRREG	GPIOA_PDDR
    #define CORE_PIN27_DDRREG	GPIOA_PDDR
    #define CORE_PIN28_DDRREG	GPIOA_PDDR
    #define CORE_PIN29_DDRREG	GPIOB_PDDR
    #define CORE_PIN30_DDRREG	GPIOB_PDDR
    #define CORE_PIN31_DDRREG	GPIOB_PDDR
    #define CORE_PIN32_DDRREG	GPIOB_PDDR
    #define CORE_PIN33_DDRREG	GPIOE_PDDR
    #define CORE_PIN34_DDRREG	GPIOE_PDDR
    #define CORE_PIN35_DDRREG	GPIOC_PDDR
    #define CORE_PIN36_DDRREG	GPIOC_PDDR
    #define CORE_PIN37_DDRREG	GPIOC_PDDR
    #define CORE_PIN38_DDRREG	GPIOC_PDDR
    #define CORE_PIN39_DDRREG	GPIOA_PDDR
    #define CORE_PIN40_DDRREG	GPIOA_PDDR
    #define CORE_PIN41_DDRREG	GPIOA_PDDR
    #define CORE_PIN42_DDRREG	GPIOA_PDDR
    #define CORE_PIN43_DDRREG	GPIOB_PDDR
    #define CORE_PIN44_DDRREG	GPIOB_PDDR
    #define CORE_PIN45_DDRREG	GPIOB_PDDR
    #define CORE_PIN46_DDRREG	GPIOB_PDDR
    #define CORE_PIN47_DDRREG	GPIOD_PDDR
    #define CORE_PIN48_DDRREG	GPIOD_PDDR
    #define CORE_PIN49_DDRREG	GPIOB_PDDR
    #define CORE_PIN50_DDRREG	GPIOB_PDDR
    #define CORE_PIN51_DDRREG	GPIOD_PDDR
    #define CORE_PIN52_DDRREG	GPIOD_PDDR
    #define CORE_PIN53_DDRREG	GPIOD_PDDR
    #define CORE_PIN54_DDRREG	GPIOD_PDDR
    #define CORE_PIN55_DDRREG	GPIOD_PDDR
    #define CORE_PIN56_DDRREG	GPIOE_PDDR
    #define CORE_PIN57_DDRREG	GPIOE_PDDR
    #define CORE_PIN58_DDRREG	GPIOE_PDDR
    #define CORE_PIN59_DDRREG	GPIOE_PDDR
    #define CORE_PIN60_DDRREG	GPIOE_PDDR
    #define CORE_PIN61_DDRREG	GPIOE_PDDR
    #define CORE_PIN62_DDRREG	GPIOE_PDDR
    #define CORE_PIN63_DDRREG	GPIOE_PDDR
    
    #define CORE_PIN0_PINREG	GPIOB_PDIR
    #define CORE_PIN1_PINREG	GPIOB_PDIR
    #define CORE_PIN2_PINREG	GPIOD_PDIR
    #define CORE_PIN3_PINREG	GPIOA_PDIR
    #define CORE_PIN4_PINREG	GPIOA_PDIR
    #define CORE_PIN5_PINREG	GPIOD_PDIR
    #define CORE_PIN6_PINREG	GPIOD_PDIR
    #define CORE_PIN7_PINREG	GPIOD_PDIR
    #define CORE_PIN8_PINREG	GPIOD_PDIR
    #define CORE_PIN9_PINREG	GPIOC_PDIR
    #define CORE_PIN10_PINREG	GPIOC_PDIR
    #define CORE_PIN11_PINREG	GPIOC_PDIR
    #define CORE_PIN12_PINREG	GPIOC_PDIR
    #define CORE_PIN13_PINREG	GPIOC_PDIR
    #define CORE_PIN14_PINREG	GPIOD_PDIR
    #define CORE_PIN15_PINREG	GPIOC_PDIR
    #define CORE_PIN16_PINREG	GPIOB_PDIR
    #define CORE_PIN17_PINREG	GPIOB_PDIR
    #define CORE_PIN18_PINREG	GPIOB_PDIR
    #define CORE_PIN19_PINREG	GPIOB_PDIR
    #define CORE_PIN20_PINREG	GPIOD_PDIR
    #define CORE_PIN21_PINREG	GPIOD_PDIR
    #define CORE_PIN22_PINREG	GPIOC_PDIR
    #define CORE_PIN23_PINREG	GPIOC_PDIR
    #define CORE_PIN24_PINREG	GPIOE_PDIR
    #define CORE_PIN25_PINREG	GPIOA_PDIR
    #define CORE_PIN26_PINREG	GPIOA_PDIR
    #define CORE_PIN27_PINREG	GPIOA_PDIR
    #define CORE_PIN28_PINREG	GPIOA_PDIR
    #define CORE_PIN29_PINREG	GPIOB_PDIR
    #define CORE_PIN30_PINREG	GPIOB_PDIR
    #define CORE_PIN31_PINREG	GPIOB_PDIR
    #define CORE_PIN32_PINREG	GPIOB_PDIR
    #define CORE_PIN33_PINREG	GPIOE_PDIR
    #define CORE_PIN34_PINREG	GPIOE_PDIR
    #define CORE_PIN35_PINREG	GPIOC_PDIR
    #define CORE_PIN36_PINREG	GPIOC_PDIR
    #define CORE_PIN37_PINREG	GPIOC_PDIR
    #define CORE_PIN38_PINREG	GPIOC_PDIR
    #define CORE_PIN39_PINREG	GPIOA_PDIR
    #define CORE_PIN40_PINREG	GPIOA_PDIR
    #define CORE_PIN41_PINREG	GPIOA_PDIR
    #define CORE_PIN42_PINREG	GPIOA_PDIR
    #define CORE_PIN43_PINREG	GPIOB_PDIR
    #define CORE_PIN44_PINREG	GPIOB_PDIR
    #define CORE_PIN45_PINREG	GPIOB_PDIR
    #define CORE_PIN46_PINREG	GPIOB_PDIR
    #define CORE_PIN47_PINREG	GPIOD_PDIR
    #define CORE_PIN48_PINREG	GPIOD_PDIR
    #define CORE_PIN49_PINREG	GPIOB_PDIR
    #define CORE_PIN50_PINREG	GPIOB_PDIR
    #define CORE_PIN51_PINREG	GPIOD_PDIR
    #define CORE_PIN52_PINREG	GPIOD_PDIR
    #define CORE_PIN53_PINREG	GPIOD_PDIR
    #define CORE_PIN54_PINREG	GPIOD_PDIR
    #define CORE_PIN55_PINREG	GPIOD_PDIR
    #define CORE_PIN56_PINREG	GPIOE_PDIR
    #define CORE_PIN57_PINREG	GPIOE_PDIR
    #define CORE_PIN58_PINREG	GPIOE_PDIR
    #define CORE_PIN59_PINREG	GPIOE_PDIR
    #define CORE_PIN60_PINREG	GPIOE_PDIR
    #define CORE_PIN61_PINREG	GPIOE_PDIR
    #define CORE_PIN62_PINREG	GPIOE_PDIR
    #define CORE_PIN63_PINREG	GPIOE_PDIR
    
    #define CORE_PIN0_CONFIG	PORTB_PCR16
    #define CORE_PIN1_CONFIG	PORTB_PCR17
    #define CORE_PIN2_CONFIG	PORTD_PCR0
    #define CORE_PIN3_CONFIG	PORTA_PCR12
    #define CORE_PIN4_CONFIG	PORTA_PCR13
    #define CORE_PIN5_CONFIG	PORTD_PCR7
    #define CORE_PIN6_CONFIG	PORTD_PCR4
    #define CORE_PIN7_CONFIG	PORTD_PCR2
    #define CORE_PIN8_CONFIG	PORTD_PCR3
    #define CORE_PIN9_CONFIG	PORTC_PCR3
    #define CORE_PIN10_CONFIG	PORTC_PCR4
    #define CORE_PIN11_CONFIG	PORTC_PCR6
    #define CORE_PIN12_CONFIG	PORTC_PCR7
    #define CORE_PIN13_CONFIG	PORTC_PCR5
    #define CORE_PIN14_CONFIG	PORTD_PCR1
    #define CORE_PIN15_CONFIG	PORTC_PCR0
    #define CORE_PIN16_CONFIG	PORTB_PCR0
    #define CORE_PIN17_CONFIG	PORTB_PCR1
    #define CORE_PIN18_CONFIG	PORTB_PCR3
    #define CORE_PIN19_CONFIG	PORTB_PCR2
    #define CORE_PIN20_CONFIG	PORTD_PCR5
    #define CORE_PIN21_CONFIG	PORTD_PCR6
    #define CORE_PIN22_CONFIG	PORTC_PCR1
    #define CORE_PIN23_CONFIG	PORTC_PCR2
    #define CORE_PIN24_CONFIG	PORTE_PCR26
    #define CORE_PIN25_CONFIG	PORTA_PCR5
    #define CORE_PIN26_CONFIG	PORTA_PCR14
    #define CORE_PIN27_CONFIG	PORTA_PCR15
    #define CORE_PIN28_CONFIG	PORTA_PCR16
    #define CORE_PIN29_CONFIG	PORTB_PCR18
    #define CORE_PIN30_CONFIG	PORTB_PCR19
    #define CORE_PIN31_CONFIG	PORTB_PCR10
    #define CORE_PIN32_CONFIG	PORTB_PCR11
    #define CORE_PIN33_CONFIG	PORTE_PCR24
    #define CORE_PIN34_CONFIG	PORTE_PCR25
    #define CORE_PIN35_CONFIG	PORTC_PCR8
    #define CORE_PIN36_CONFIG	PORTC_PCR9
    #define CORE_PIN37_CONFIG	PORTC_PCR10
    #define CORE_PIN38_CONFIG	PORTC_PCR11
    #define CORE_PIN39_CONFIG	PORTA_PCR17
    #define CORE_PIN40_CONFIG	PORTA_PCR28
    #define CORE_PIN41_CONFIG	PORTA_PCR29
    #define CORE_PIN42_CONFIG	PORTA_PCR26
    #define CORE_PIN43_CONFIG	PORTB_PCR20
    #define CORE_PIN44_CONFIG	PORTB_PCR22
    #define CORE_PIN45_CONFIG	PORTB_PCR23
    #define CORE_PIN46_CONFIG	PORTB_PCR21
    #define CORE_PIN47_CONFIG	PORTD_PCR8
    #define CORE_PIN48_CONFIG	PORTD_PCR9
    #define CORE_PIN49_CONFIG	PORTB_PCR4
    #define CORE_PIN50_CONFIG	PORTB_PCR5
    #define CORE_PIN51_CONFIG	PORTD_PCR14
    #define CORE_PIN52_CONFIG	PORTD_PCR13
    #define CORE_PIN53_CONFIG	PORTD_PCR12
    #define CORE_PIN54_CONFIG	PORTD_PCR15
    #define CORE_PIN55_CONFIG	PORTD_PCR11
    #define CORE_PIN56_CONFIG	PORTE_PCR10
    #define CORE_PIN57_CONFIG	PORTE_PCR11
    #define CORE_PIN58_CONFIG	PORTE_PCR0
    #define CORE_PIN59_CONFIG	PORTE_PCR1
    #define CORE_PIN60_CONFIG	PORTE_PCR2
    #define CORE_PIN61_CONFIG	PORTE_PCR3
    #define CORE_PIN62_CONFIG	PORTE_PCR4
    #define CORE_PIN63_CONFIG	PORTE_PCR5
    
    #define CORE_ADC0_PIN		14
    #define CORE_ADC1_PIN		15
    #define CORE_ADC2_PIN		16
    #define CORE_ADC3_PIN		17
    #define CORE_ADC4_PIN		18
    #define CORE_ADC5_PIN		19
    #define CORE_ADC6_PIN		20
    #define CORE_ADC7_PIN		21
    #define CORE_ADC8_PIN		22
    #define CORE_ADC9_PIN		23
    #define CORE_ADC10_PIN		64
    #define CORE_ADC11_PIN		65
    #define CORE_ADC12_PIN		31
    #define CORE_ADC13_PIN		32
    #define CORE_ADC14_PIN		33
    #define CORE_ADC15_PIN		34
    #define CORE_ADC16_PIN		35
    #define CORE_ADC17_PIN		36
    #define CORE_ADC18_PIN		37
    #define CORE_ADC19_PIN		38
    #define CORE_ADC20_PIN		39
    #define CORE_ADC21_PIN		66
    #define CORE_ADC22_PIN		67
    #define CORE_ADC23_PIN		49
    #define CORE_ADC24_PIN		50
    #define CORE_ADC25_PIN		68
    #define CORE_ADC26_PIN		69
    
    #define CORE_RXD0_PIN		0
    #define CORE_TXD0_PIN		1
    #define CORE_RXD1_PIN		9
    #define CORE_TXD1_PIN		10
    #define CORE_RXD2_PIN		7
    #define CORE_TXD2_PIN		8
    #define CORE_RXD3_PIN		31
    #define CORE_TXD3_PIN		32
    #define CORE_RXD4_PIN		34
    #define CORE_TXD4_PIN		33
    
    #define CORE_INT0_PIN		0
    #define CORE_INT1_PIN		1
    #define CORE_INT2_PIN		2
    #define CORE_INT3_PIN		3
    #define CORE_INT4_PIN		4
    #define CORE_INT5_PIN		5
    #define CORE_INT6_PIN		6
    #define CORE_INT7_PIN		7
    #define CORE_INT8_PIN		8
    #define CORE_INT9_PIN		9
    #define CORE_INT10_PIN		10
    #define CORE_INT11_PIN		11
    #define CORE_INT12_PIN		12
    #define CORE_INT13_PIN		13
    #define CORE_INT14_PIN		14
    #define CORE_INT15_PIN		15
    #define CORE_INT16_PIN		16
    #define CORE_INT17_PIN		17
    #define CORE_INT18_PIN		18
    #define CORE_INT19_PIN		19
    #define CORE_INT20_PIN		20
    #define CORE_INT21_PIN		21
    #define CORE_INT22_PIN		22
    #define CORE_INT23_PIN		23
    #define CORE_INT24_PIN		24
    #define CORE_INT25_PIN		25
    #define CORE_INT26_PIN		26
    #define CORE_INT27_PIN		27
    #define CORE_INT28_PIN		28
    #define CORE_INT29_PIN		29
    #define CORE_INT30_PIN		30
    #define CORE_INT31_PIN		31
    #define CORE_INT32_PIN		32
    #define CORE_INT33_PIN		33
    #define CORE_INT34_PIN		34
    #define CORE_INT35_PIN		35
    #define CORE_INT36_PIN		36
    #define CORE_INT37_PIN		37
    #define CORE_INT38_PIN		38
    #define CORE_INT39_PIN		39
    #define CORE_INT40_PIN		40
    #define CORE_INT41_PIN		41
    #define CORE_INT42_PIN		42
    #define CORE_INT43_PIN		43
    #define CORE_INT44_PIN		44
    #define CORE_INT45_PIN		45
    #define CORE_INT46_PIN		46
    #define CORE_INT47_PIN		47
    #define CORE_INT48_PIN		48
    #define CORE_INT49_PIN		49
    #define CORE_INT50_PIN		50
    #define CORE_INT51_PIN		51
    #define CORE_INT52_PIN		52
    #define CORE_INT53_PIN		53
    #define CORE_INT54_PIN		54
    #define CORE_INT55_PIN		55
    #define CORE_INT56_PIN		56
    #define CORE_INT57_PIN		57
    #define CORE_INT58_PIN		58
    #define CORE_INT59_PIN		59
    #define CORE_INT60_PIN		60
    #define CORE_INT61_PIN		61
    #define CORE_INT62_PIN		62
    #define CORE_INT63_PIN		63
    #define CORE_INT_EVERY_PIN	1
    
    
    
    
    
    #define CORE_FTM0_CH0_PIN	22
    #define CORE_FTM0_CH1_PIN	23
    #define CORE_FTM0_CH2_PIN	 9
    #define CORE_FTM0_CH3_PIN	10
    #define CORE_FTM0_CH4_PIN	 6
    #define CORE_FTM0_CH5_PIN	20
    #define CORE_FTM0_CH6_PIN	21
    #define CORE_FTM0_CH7_PIN	 5
    #define CORE_FTM1_CH0_PIN	 3
    #define CORE_FTM1_CH1_PIN	 4
    #define CORE_FTM2_CH0_PIN	29
    #define CORE_FTM2_CH1_PIN	30
    #define CORE_FTM3_CH0_PIN	 2
    #define CORE_FTM3_CH1_PIN	14
    #define CORE_FTM3_CH2_PIN	 7
    #define CORE_FTM3_CH3_PIN	 8
    #define CORE_FTM3_CH4_PIN	35
    #define CORE_FTM3_CH5_PIN	36
    #define CORE_FTM3_CH6_PIN	37
    #define CORE_FTM3_CH7_PIN	38
    #define CORE_TPM1_CH0_PIN	16
    #define CORE_TPM1_CH1_PIN	17
    
    
    
    #ifdef __cplusplus
    extern "C" {
    #endif
    
    void digitalWrite(uint8_t pin, uint8_t val);
    static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused));
    static inline void digitalWriteFast(uint8_t pin, uint8_t val)
    {
    	if (__builtin_constant_p(pin)) {
    		if (val) {
    			if (pin == 0) {
    				CORE_PIN0_PORTSET = CORE_PIN0_BITMASK;
    			} else if (pin == 1) {
    				CORE_PIN1_PORTSET = CORE_PIN1_BITMASK;
    			} else if (pin == 2) {
    				CORE_PIN2_PORTSET = CORE_PIN2_BITMASK;
    			} else if (pin == 3) {
    				CORE_PIN3_PORTSET = CORE_PIN3_BITMASK;
    			} else if (pin == 4) {
    				CORE_PIN4_PORTSET = CORE_PIN4_BITMASK;
    			} else if (pin == 5) {
    				CORE_PIN5_PORTSET = CORE_PIN5_BITMASK;
    			} else if (pin == 6) {
    				CORE_PIN6_PORTSET = CORE_PIN6_BITMASK;
    			} else if (pin == 7) {
    				CORE_PIN7_PORTSET = CORE_PIN7_BITMASK;
    			} else if (pin == 8) {
    				CORE_PIN8_PORTSET = CORE_PIN8_BITMASK;
    			} else if (pin == 9) {
    				CORE_PIN9_PORTSET = CORE_PIN9_BITMASK;
    			} else if (pin == 10) {
    				CORE_PIN10_PORTSET = CORE_PIN10_BITMASK;
    			} else if (pin == 11) {
    				CORE_PIN11_PORTSET = CORE_PIN11_BITMASK;
    			} else if (pin == 12) {
    				CORE_PIN12_PORTSET = CORE_PIN12_BITMASK;
    			} else if (pin == 13) {
    				CORE_PIN13_PORTSET = CORE_PIN13_BITMASK;
    			} else if (pin == 14) {
    				CORE_PIN14_PORTSET = CORE_PIN14_BITMASK;
    			} else if (pin == 15) {
    				CORE_PIN15_PORTSET = CORE_PIN15_BITMASK;
    			} else if (pin == 16) {
    				CORE_PIN16_PORTSET = CORE_PIN16_BITMASK;
    			} else if (pin == 17) {
    				CORE_PIN17_PORTSET = CORE_PIN17_BITMASK;
    			} else if (pin == 18) {
    				CORE_PIN18_PORTSET = CORE_PIN18_BITMASK;
    			} else if (pin == 19) {
    				CORE_PIN19_PORTSET = CORE_PIN19_BITMASK;
    			} else if (pin == 20) {
    				CORE_PIN20_PORTSET = CORE_PIN20_BITMASK;
    			} else if (pin == 21) {
    				CORE_PIN21_PORTSET = CORE_PIN21_BITMASK;
    			} else if (pin == 22) {
    				CORE_PIN22_PORTSET = CORE_PIN22_BITMASK;
    			} else if (pin == 23) {
    				CORE_PIN23_PORTSET = CORE_PIN23_BITMASK;
    			} else if (pin == 24) {
    				CORE_PIN24_PORTSET = CORE_PIN24_BITMASK;
    			} else if (pin == 25) {
    				CORE_PIN25_PORTSET = CORE_PIN25_BITMASK;
    			} else if (pin == 26) {
    				CORE_PIN26_PORTSET = CORE_PIN26_BITMASK;
    			}
    			#if defined(CORE_PIN27_PORTSET)
    			  else if (pin == 27) {
    				CORE_PIN27_PORTSET = CORE_PIN27_BITMASK;
    			} else if (pin == 28) {
    				CORE_PIN28_PORTSET = CORE_PIN28_BITMASK;
    			} else if (pin == 29) {
    				CORE_PIN29_PORTSET = CORE_PIN29_BITMASK;
    			} else if (pin == 30) {
    				CORE_PIN30_PORTSET = CORE_PIN30_BITMASK;
    			} else if (pin == 31) {
    				CORE_PIN31_PORTSET = CORE_PIN31_BITMASK;
    			} else if (pin == 32) {
    				CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;
    			} else if (pin == 33) {
    				CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;
    			}
    			#endif
    			#if defined(CORE_PIN34_PORTSET)
    			  else if (pin == 34) {
    				CORE_PIN34_PORTSET = CORE_PIN34_BITMASK;
    			} else if (pin == 35) {
    				CORE_PIN35_PORTSET = CORE_PIN35_BITMASK;
    			} else if (pin == 36) {
    				CORE_PIN36_PORTSET = CORE_PIN36_BITMASK;
    			} else if (pin == 37) {
    				CORE_PIN37_PORTSET = CORE_PIN37_BITMASK;
    			} else if (pin == 38) {
    				CORE_PIN38_PORTSET = CORE_PIN38_BITMASK;
    			} else if (pin == 39) {
    				CORE_PIN39_PORTSET = CORE_PIN39_BITMASK;
    			} else if (pin == 40) {
    				CORE_PIN40_PORTSET = CORE_PIN40_BITMASK;
    			} else if (pin == 41) {
    				CORE_PIN41_PORTSET = CORE_PIN41_BITMASK;
    			} else if (pin == 42) {
    				CORE_PIN42_PORTSET = CORE_PIN42_BITMASK;
    			} else if (pin == 43) {
    				CORE_PIN43_PORTSET = CORE_PIN43_BITMASK;
    			} else if (pin == 44) {
    				CORE_PIN44_PORTSET = CORE_PIN44_BITMASK;
    			} else if (pin == 45) {
    				CORE_PIN45_PORTSET = CORE_PIN45_BITMASK;
    			} else if (pin == 46) {
    				CORE_PIN46_PORTSET = CORE_PIN46_BITMASK;
    			} else if (pin == 47) {
    				CORE_PIN47_PORTSET = CORE_PIN47_BITMASK;
    			} else if (pin == 48) {
    				CORE_PIN48_PORTSET = CORE_PIN48_BITMASK;
    			} else if (pin == 49) {
    				CORE_PIN49_PORTSET = CORE_PIN49_BITMASK;
    			} else if (pin == 50) {
    				CORE_PIN50_PORTSET = CORE_PIN50_BITMASK;
    			} else if (pin == 51) {
    				CORE_PIN51_PORTSET = CORE_PIN51_BITMASK;
    			} else if (pin == 52) {
    				CORE_PIN52_PORTSET = CORE_PIN52_BITMASK;
    			} else if (pin == 53) {
    				CORE_PIN53_PORTSET = CORE_PIN53_BITMASK;
    			} else if (pin == 54) {
    				CORE_PIN54_PORTSET = CORE_PIN54_BITMASK;
    			} else if (pin == 55) {
    				CORE_PIN55_PORTSET = CORE_PIN55_BITMASK;
    			} else if (pin == 56) {
    				CORE_PIN56_PORTSET = CORE_PIN56_BITMASK;
    			} else if (pin == 57) {
    				CORE_PIN57_PORTSET = CORE_PIN57_BITMASK;
    			} else if (pin == 58) {
    				CORE_PIN58_PORTSET = CORE_PIN58_BITMASK;
    			} else if (pin == 59) {
    				CORE_PIN59_PORTSET = CORE_PIN59_BITMASK;
    			} else if (pin == 60) {
    				CORE_PIN60_PORTSET = CORE_PIN60_BITMASK;
    			} else if (pin == 61) {
    				CORE_PIN61_PORTSET = CORE_PIN61_BITMASK;
    			} else if (pin == 62) {
    				CORE_PIN62_PORTSET = CORE_PIN62_BITMASK;
    			} else if (pin == 63) {
    				CORE_PIN63_PORTSET = CORE_PIN63_BITMASK;
    			} else if (pin == 72) {
    				CORE_PIN72_PORTSET = CORE_PIN72_BITMASK;
    			} else if (pin == 72) {
    				CORE_PIN73_PORTSET = CORE_PIN73_BITMASK;
    			} else if (pin == 72) {
    				CORE_PIN74_PORTSET = CORE_PIN74_BITMASK;
    			}
    			#endif
    		} else {
    			if (pin == 0) {
    				CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;
    			} else if (pin == 1) {
    				CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK;
    			} else if (pin == 2) {
    				CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK;
    			} else if (pin == 3) {
    				CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK;
    			} else if (pin == 4) {
    				CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK;
    			} else if (pin == 5) {
    				CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK;
    			} else if (pin == 6) {
    				CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK;
    			} else if (pin == 7) {
    				CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK;
    			} else if (pin == 8) {
    				CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK;
    			} else if (pin == 9) {
    				CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK;
    			} else if (pin == 10) {
    				CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK;
    			} else if (pin == 11) {
    				CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK;
    			} else if (pin == 12) {
    				CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK;
    			} else if (pin == 13) {
    				CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK;
    			} else if (pin == 14) {
    				CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK;
    			} else if (pin == 15) {
    				CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK;
    			} else if (pin == 16) {
    				CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK;
    			} else if (pin == 17) {
    				CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK;
    			} else if (pin == 18) {
    				CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK;
    			} else if (pin == 19) {
    				CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK;
    			} else if (pin == 20) {
    				CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK;
    			} else if (pin == 21) {
    				CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK;
    			} else if (pin == 22) {
    				CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK;
    			} else if (pin == 23) {
    				CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK;
    			} else if (pin == 24) {
    				CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK;
    			} else if (pin == 25) {
    				CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK;
    			} else if (pin == 26) {
    				CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK;
    			}
    			#if defined(CORE_PIN27_PORTCLEAR)
    			  else if (pin == 27) {
    				CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK;
    			} else if (pin == 28) {
    				CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK;
    			} else if (pin == 29) {
    				CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK;
    			} else if (pin == 30) {
    				CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK;
    			} else if (pin == 31) {
    				CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK;
    			} else if (pin == 32) {
    				CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;
    			} else if (pin == 33) {
    				CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;
    			}
    			#endif
    			#if defined(CORE_PIN34_PORTCLEAR)
    			  else if (pin == 34) {
    				CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK;
    			} else if (pin == 35) {
    				CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK;
    			} else if (pin == 36) {
    				CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK;
    			} else if (pin == 37) {
    				CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK;
    			} else if (pin == 38) {
    				CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK;
    			} else if (pin == 39) {
    				CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK;
    			} else if (pin == 40) {
    				CORE_PIN40_PORTCLEAR = CORE_PIN40_BITMASK;
    			} else if (pin == 41) {
    				CORE_PIN41_PORTCLEAR = CORE_PIN41_BITMASK;
    			} else if (pin == 42) {
    				CORE_PIN42_PORTCLEAR = CORE_PIN42_BITMASK;
    			} else if (pin == 43) {
    				CORE_PIN43_PORTCLEAR = CORE_PIN43_BITMASK;
    			} else if (pin == 44) {
    				CORE_PIN44_PORTCLEAR = CORE_PIN44_BITMASK;
    			} else if (pin == 45) {
    				CORE_PIN45_PORTCLEAR = CORE_PIN45_BITMASK;
    			} else if (pin == 46) {
    				CORE_PIN46_PORTCLEAR = CORE_PIN46_BITMASK;
    			} else if (pin == 47) {
    				CORE_PIN47_PORTCLEAR = CORE_PIN47_BITMASK;
    			} else if (pin == 48) {
    				CORE_PIN48_PORTCLEAR = CORE_PIN48_BITMASK;
    			} else if (pin == 49) {
    				CORE_PIN49_PORTCLEAR = CORE_PIN49_BITMASK;
    			} else if (pin == 50) {
    				CORE_PIN50_PORTCLEAR = CORE_PIN50_BITMASK;
    			} else if (pin == 51) {
    				CORE_PIN51_PORTCLEAR = CORE_PIN51_BITMASK;
    			} else if (pin == 52) {
    				CORE_PIN52_PORTCLEAR = CORE_PIN52_BITMASK;
    			} else if (pin == 53) {
    				CORE_PIN53_PORTCLEAR = CORE_PIN53_BITMASK;
    			} else if (pin == 54) {
    				CORE_PIN54_PORTCLEAR = CORE_PIN54_BITMASK;
    			} else if (pin == 55) {
    				CORE_PIN55_PORTCLEAR = CORE_PIN55_BITMASK;
    			} else if (pin == 56) {
    				CORE_PIN56_PORTCLEAR = CORE_PIN56_BITMASK;
    			} else if (pin == 57) {
    				CORE_PIN57_PORTCLEAR = CORE_PIN57_BITMASK;
    			} else if (pin == 58) {
    				CORE_PIN58_PORTCLEAR = CORE_PIN58_BITMASK;
    			} else if (pin == 59) {
    				CORE_PIN59_PORTCLEAR = CORE_PIN59_BITMASK;
    			} else if (pin == 60) {
    				CORE_PIN60_PORTCLEAR = CORE_PIN60_BITMASK;
    			} else if (pin == 61) {
    				CORE_PIN61_PORTCLEAR = CORE_PIN61_BITMASK;
    			} else if (pin == 62) {
    				CORE_PIN62_PORTCLEAR = CORE_PIN62_BITMASK;
    			} else if (pin == 63) {
    				CORE_PIN63_PORTCLEAR = CORE_PIN63_BITMASK;
    			} else if (pin == 72) {
    				CORE_PIN72_PORTCLEAR = CORE_PIN72_BITMASK;
    			} else if (pin == 73) {
    				CORE_PIN73_PORTCLEAR = CORE_PIN73_BITMASK;
    			} else if (pin == 74) {
    				CORE_PIN74_PORTCLEAR = CORE_PIN74_BITMASK;
    			}
    			#endif
    		}
    	} else {
    		if (val) {
    			*portSetRegister(pin) = digitalPinToBitMask(pin);
    		} else {
    			*portClearRegister(pin) = digitalPinToBitMask(pin);
    		}
    	}
    }
    
    uint8_t digitalRead(uint8_t pin);
    static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused));
    static inline uint8_t digitalReadFast(uint8_t pin)
    {
    	if (__builtin_constant_p(pin)) {
    		if (pin == 0) {
    			return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0;
    		} else if (pin == 1) {
    			return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0;
    		} else if (pin == 2) {
    			return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0;
    		} else if (pin == 3) {
    			return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0;
    		} else if (pin == 4) {
    			return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0;
    		} else if (pin == 5) {
    			return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0;
    		} else if (pin == 6) {
    			return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0;
    		} else if (pin == 7) {
    			return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0;
    		} else if (pin == 8) {
    			return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0;
    		} else if (pin == 9) {
    			return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0;
    		} else if (pin == 10) {
    			return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0;
    		} else if (pin == 11) {
    			return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0;
    		} else if (pin == 12) {
    			return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0;
    		} else if (pin == 13) {
    			return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0;
    		} else if (pin == 14) {
    			return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0;
    		} else if (pin == 15) {
    			return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0;
    		} else if (pin == 16) {
    			return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0;
    		} else if (pin == 17) {
    			return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0;
    		} else if (pin == 18) {
    			return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0;
    		} else if (pin == 19) {
    			return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0;
    		} else if (pin == 20) {
    			return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0;
    		} else if (pin == 21) {
    			return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0;
    		} else if (pin == 22) {
    			return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0;
    		} else if (pin == 23) {
    			return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0;
    		} else if (pin == 24) {
    			return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0;
    		} else if (pin == 25) {
    			return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0;
    		} else if (pin == 26) {
    			return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0;
    		}
    		#if defined(CORE_PIN27_PINREG)
    		  else if (pin == 27) {
    			return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0;
    		} else if (pin == 28) {
    			return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0;
    		} else if (pin == 29) {
    			return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0;
    		} else if (pin == 30) {
    			return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0;
    		} else if (pin == 31) {
    			return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0;
    		} else if (pin == 32) {
    			return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;
    		} else if (pin == 33) {
    			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;
    		}
    		#endif
    		#if defined(CORE_PIN34_PINREG)
    		  else if (pin == 34) {
    			return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0;
    		} else if (pin == 35) {
    			return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0;
    		} else if (pin == 36) {
    			return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0;
    		} else if (pin == 37) {
    			return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0;
    		} else if (pin == 38) {
    			return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0;
    		} else if (pin == 39) {
    			return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0;
    		} else if (pin == 40) {
    			return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0;
    		} else if (pin == 41) {
    			return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0;
    		} else if (pin == 42) {
    			return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0;
    		} else if (pin == 43) {
    			return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0;
    		} else if (pin == 44) {
    			return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0;
    		} else if (pin == 45) {
    			return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0;
    		} else if (pin == 46) {
    			return (CORE_PIN46_PINREG & CORE_PIN46_BITMASK) ? 1 : 0;
    		} else if (pin == 47) {
    			return (CORE_PIN47_PINREG & CORE_PIN47_BITMASK) ? 1 : 0;
    		} else if (pin == 48) {
    			return (CORE_PIN48_PINREG & CORE_PIN48_BITMASK) ? 1 : 0;
    		} else if (pin == 49) {
    			return (CORE_PIN49_PINREG & CORE_PIN49_BITMASK) ? 1 : 0;
    		} else if (pin == 50) {
    			return (CORE_PIN50_PINREG & CORE_PIN50_BITMASK) ? 1 : 0;
    		} else if (pin == 51) {
    			return (CORE_PIN51_PINREG & CORE_PIN51_BITMASK) ? 1 : 0;
    		} else if (pin == 52) {
    			return (CORE_PIN52_PINREG & CORE_PIN52_BITMASK) ? 1 : 0;
    		} else if (pin == 53) {
    			return (CORE_PIN53_PINREG & CORE_PIN53_BITMASK) ? 1 : 0;
    		} else if (pin == 54) {
    			return (CORE_PIN54_PINREG & CORE_PIN54_BITMASK) ? 1 : 0;
    		} else if (pin == 55) {
    			return (CORE_PIN55_PINREG & CORE_PIN55_BITMASK) ? 1 : 0;
    		} else if (pin == 56) {
    			return (CORE_PIN56_PINREG & CORE_PIN56_BITMASK) ? 1 : 0;
    		} else if (pin == 57) {
    			return (CORE_PIN57_PINREG & CORE_PIN57_BITMASK) ? 1 : 0;
    		} else if (pin == 58) {
    			return (CORE_PIN58_PINREG & CORE_PIN58_BITMASK) ? 1 : 0;
    		} else if (pin == 59) {
    			return (CORE_PIN59_PINREG & CORE_PIN59_BITMASK) ? 1 : 0;
    		} else if (pin == 60) {
    			return (CORE_PIN60_PINREG & CORE_PIN60_BITMASK) ? 1 : 0;
    		} else if (pin == 61) {
    			return (CORE_PIN61_PINREG & CORE_PIN61_BITMASK) ? 1 : 0;
    		} else if (pin == 62) {
    			return (CORE_PIN62_PINREG & CORE_PIN62_BITMASK) ? 1 : 0;
    		} else if (pin == 63) {
    			return (CORE_PIN63_PINREG & CORE_PIN63_BITMASK) ? 1 : 0;
    		} else if (pin == 72) {
    			return (CORE_PIN72_PINREG & CORE_PIN72_BITMASK) ? 1 : 0;
    		} else if (pin == 73) {
    			return (CORE_PIN73_PINREG & CORE_PIN73_BITMASK) ? 1 : 0;
    		} else if (pin == 74) {
    			return (CORE_PIN74_PINREG & CORE_PIN74_BITMASK) ? 1 : 0;
    		}
    		#endif
    		  else {
    			return 0;
    		}
    	} else {
    		#if defined(KINETISK)
    		return *portInputRegister(pin);
    		#else
    		return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0;
    		#endif
    	}
    }
    
    
    void pinMode(uint8_t pin, uint8_t mode);
    void init_pins(void);
    void analogWrite(uint8_t pin, int val);
    uint32_t analogWriteRes(uint32_t bits);
    static inline uint32_t analogWriteResolution(uint32_t bits) { return analogWriteRes(bits); }
    void analogWriteFrequency(uint8_t pin, float frequency);
    void analogWriteDAC0(int val);
    void analogWriteDAC1(int val);
    #ifdef __cplusplus
    void attachInterruptVector(IRQ_NUMBER_t irq, void (*function)(void));
    #else
    void attachInterruptVector(enum IRQ_NUMBER_t irq, void (*function)(void));
    #endif
    void attachInterrupt(uint8_t pin, void (*function)(void), int mode);
    void detachInterrupt(uint8_t pin);
    void _init_Teensyduino_internal_(void);
    
    int analogRead(uint8_t pin);
    void analogReference(uint8_t type);
    void analogReadRes(unsigned int bits);
    static inline void analogReadResolution(unsigned int bits) { analogReadRes(bits); }
    void analogReadAveraging(unsigned int num);
    void analog_init(void);
    
    
    
    #define DEFAULT         0
    #define INTERNAL        2
    #define INTERNAL1V2     2
    #define INTERNAL1V1     2
    #define EXTERNAL        0
    
    
    
    
    int touchRead(uint8_t pin);
    
    
    static inline void shiftOut(uint8_t, uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));
    extern void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) __attribute__((noinline));
    extern void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));
    extern void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));
    
    static inline void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)
    {
            if (__builtin_constant_p(bitOrder)) {
                    if (bitOrder == LSBFIRST) {
                            shiftOut_lsbFirst(dataPin, clockPin, value);
                    } else {
                            shiftOut_msbFirst(dataPin, clockPin, value);
                    }
            } else {
                    _shiftOut(dataPin, clockPin, bitOrder, value);
            }
    }
    
    static inline uint8_t shiftIn(uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));
    extern uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) __attribute__((noinline));
    extern uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));
    extern uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));
    
    static inline uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)
    {
            if (__builtin_constant_p(bitOrder)) {
                    if (bitOrder == LSBFIRST) {
                            return shiftIn_lsbFirst(dataPin, clockPin);
                    } else {
                            return shiftIn_msbFirst(dataPin, clockPin);
                    }
            } else {
                    return _shiftIn(dataPin, clockPin, bitOrder);
            }
    }
    
    void _reboot_Teensyduino_(void) __attribute__((noreturn));
    void _restart_Teensyduino_(void) __attribute__((noreturn));
    
    void yield(void);
    
    void delay(uint32_t msec);
    
    extern volatile uint32_t systick_millis_count;
    
    static inline uint32_t millis(void) __attribute__((always_inline, unused));
    static inline uint32_t millis(void)
    {
    	// Reading a volatile variable to another volatile
    	// seems redundant, but isn't for some cases.
    	// Eventually this should probably be replaced by a
    	// proper memory barrier or other technique.  Please
    	// do not remove this "redundant" code without
    	// carefully verifying the case mentioned here:
    	//
    	// https://forum.pjrc.com/threads/17469-millis%28%29-on-teensy-3?p=104924&viewfull=1#post104924
    	//
    	volatile uint32_t ret = systick_millis_count; // single aligned 32 bit is atomic
    	return ret;
    }
    
    uint32_t micros(void);
    
    static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));
    static inline void delayMicroseconds(uint32_t usec)
    {
    #if F_CPU == 240000000
    	uint32_t n = usec * 80;
    #elif F_CPU == 216000000
    	uint32_t n = usec * 72;
    #elif F_CPU == 192000000
    	uint32_t n = usec * 64;
    #elif F_CPU == 180000000
    	uint32_t n = usec * 60;
    #elif F_CPU == 168000000
    	uint32_t n = usec * 56;
    #elif F_CPU == 144000000
    	uint32_t n = usec * 48;
    #elif F_CPU == 120000000
    	uint32_t n = usec * 40;
    #elif F_CPU == 96000000
    	uint32_t n = usec << 5;
    #elif F_CPU == 72000000
    	uint32_t n = usec * 24;
    #elif F_CPU == 48000000
    	uint32_t n = usec << 4;
    #elif F_CPU == 24000000
    	uint32_t n = usec << 3;
    #elif F_CPU == 16000000
    	uint32_t n = usec << 2;
    #elif F_CPU == 8000000
    	uint32_t n = usec << 1;
    #elif F_CPU == 4000000
    	uint32_t n = usec;
    #elif F_CPU == 2000000
    	uint32_t n = usec >> 1;
    #endif
        // changed because a delay of 1 micro Sec @ 2MHz will be 0
    	if (n == 0) return;
    	__asm__ volatile(
    		"L_%=_delayMicroseconds:"		"\n\t"
    #if F_CPU < 24000000
    		"nop"					"\n\t"
    #endif
    #ifdef KINETISL
    		"sub    %0, #1"				"\n\t"
    #else
    		"subs   %0, #1"				"\n\t"
    #endif
    		"bne    L_%=_delayMicroseconds"		"\n"
    		: "+r" (n) :
    	);
    }
    
    #ifdef __cplusplus
    }
    #endif
    
    
    
    
    
    
    
    
    #ifdef __cplusplus
    extern "C" {
    #endif
    unsigned long rtc_get(void);
    void rtc_set(unsigned long t);
    void rtc_compensate(int adjust);
    #ifdef __cplusplus
    }
    class teensy3_clock_class
    {
    public:
    	static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); }
    	static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); }
    	static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); }
    };
    extern teensy3_clock_class Teensy3Clock;
    #endif
    
    
    
    
    #endif

  20. #45
    Senior Member brtaylor's Avatar
    Join Date
    Mar 2016
    Location
    Portland, OR
    Posts
    584
    Huh, I haven't been able to duplicate the freezing yet, but I think you would need to configure the pins in pins_teensy.c around line 106.

  21. #46
    Member
    Join Date
    Aug 2018
    Location
    Fort Worth, TX
    Posts
    38
    Quote Originally Posted by brtaylor View Post
    Huh, I haven't been able to duplicate the freezing yet, but I think you would need to configure the pins in pins_teensy.c around line 106.
    Haha, that would be correct! Thanks, Brian. I added the following after line 106 of pins_teensy.c (still just working with these three pins):

    Code:
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN73_PORTREG, CORE_PIN73_BIT), &CORE_PIN73_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN74_PORTREG, CORE_PIN74_BIT), &CORE_PIN74_CONFIG},  // new
    I also double-checked that the control registers were defined for the new pins, and they are (in kinetis.h).

    Same symptoms currently, so I'll keep digging later.

  22. #47
    Member
    Join Date
    Aug 2018
    Location
    Fort Worth, TX
    Posts
    38
    More info: I have tested pins 72-74, and 95-99. All pins still freeze the processor.

    Current info below:

    core_pins.h (do NOT use my old posts, I found an error and cannot edit those posts)
    Code:
    /* Extended pin definitions for standalone MK66 projects compatible with the Teensy 3.6 toolchain.
     * Based on Teensyduino Core Library - core_pins.h, V1.44
     * Copyright (c) 2017 PJRC.COM, LLC.
     
     * No affiliation with PJRC, no warranty or support expressed or implied.
     * https://forum.pjrc.com/threads/54114-Extended-Pin-Numbering
    */
    
    #ifndef _core_pins_h_
    #define _core_pins_h_
    
    #include "kinetis.h"
    #include "pins_arduino.h"
    
    #define HIGH		1
    #define LOW		0
    #define INPUT		0
    #define OUTPUT		1
    #define INPUT_PULLUP	2
    #define INPUT_PULLDOWN   3
    #define OUTPUT_OPENDRAIN 4
    #define INPUT_DISABLE   5
    #define LSBFIRST	0
    #define MSBFIRST	1
    #define _BV(n)		(1<<(n))
    #define CHANGE		4
    #define FALLING		2
    #define RISING		3
    
    
    #if defined(__MK66FX1M0__)
    #define CORE_NUM_TOTAL_PINS     100	// up from 64; double-check that these are all available
    #define CORE_NUM_DIGITAL        100	// up from 64; double-check that these are all available
    #define CORE_NUM_INTERRUPT      64	// need to research interrupt capabilities
    #define CORE_NUM_ANALOG         36  // double-check that these are all available
    #define CORE_NUM_PWM            22	// haven't looked at this
    #else 
    	#error "Incorrect processor selected! This library only compatible with NXP MK66/Teensy 3.6!"  // Guarantees that this library extension is not used with any non-target processors
    #endif
    
    // These MAX_PIN_PORTx values have the highest Kinetis pin index
    // that is used for a given port.
    #define CORE_MAX_PIN_PORTA        29
    #define CORE_MAX_PIN_PORTB        23
    #define CORE_MAX_PIN_PORTC        19	// Up from 11
    #define CORE_MAX_PIN_PORTD        15
    #define CORE_MAX_PIN_PORTE        28	// Up from 26
    
    //---- Begin new definitions
    // DO NOT DEFINE PTA0-4
    // 64-69 already defined in pins_arduino.h
    #define PTA5			25
    #define PTA6			72 // new
    #define PTA7			73 // new
    #define PTA8			74 // new
    #define PTA9			75 // new
    #define PTA10			76 // new
    #define PTA11			77 // new
    #define PTA12			3
    #define PTA13			4
    #define PTA14			26
    #define PTA15			27
    #define PTA16			28
    #define PTA17			39
    #define PTA24			78 // new
    #define PTA25			79 // new
    #define PTA26			42
    #define PTA27			80 // new
    #define PTA28			40
    #define PTA29			41
    #define PTB0			16
    #define PTB1			17
    #define PTB2			19
    #define PTB3			18
    #define PTB4			49
    #define PTB5			50
    #define PTB6			81 // new
    #define PTB7			82 // new
    #define PTB8			83 // new
    #define PTB9			84 // new
    #define PTB10			31
    #define PTB11			32
    #define PTB16			0
    #define PTB17			1
    #define PTB18			29
    #define PTB19			30
    #define PTB20			43
    #define PTB21			46
    #define PTB22			44
    #define PTB23			45
    #define PTC0			15
    #define PTC1			22
    #define PTC2			23
    #define PTC3			9
    #define PTC4			10
    #define PTC5			13
    #define PTC6			11
    #define PTC7			12
    #define PTC8			35
    #define PTC9			36
    #define PTC10			37
    #define PTC11			38
    #define PTC12			85 // new
    #define PTC13			86 // new
    #define PTC14			87 // new
    #define PTC15			88 // new
    #define PTC16			89 // new
    #define PTC17			90 // new
    #define PTC18			91 // new
    #define PTC19			92 // new
    #define PTD0			2
    #define PTD1			14
    #define PTD2			7
    #define PTD3			8
    #define PTD4			6
    #define PTD5			20
    #define PTD6			21
    #define PTD7			5
    #define PTD8			47
    #define PTD9			48
    #define PTD10			93 // new
    #define PTD11			55
    #define PTD12			53
    #define PTD13			52
    #define PTD14			51
    #define PTD15			54
    //#define PTE0			N/A Built In SD
    //#define PTE1			N/A Built In SD
    //#define PTE2			N/A Built In SD
    //#define PTE3			N/A Built In SD
    //#define PTE4			N/A Built In SD
    //#define PTE5			N/A Built In SD
    //#define PTE6			000  DO NOT DEFINE
    #define PTE7			94 // new
    #define PTE8			95 // new
    #define PTE9			96 // new
    #define PTE10			56
    #define PTE11			57
    #define PTE12			97 // new
    #define PTE24			33
    #define PTE25			34
    #define PTE26			24
    #define PTE27			98 // new
    #define PTE28			99 // new
    
    
    // PTA6
    #define CORE_PIN72_BIT		6
    #define CORE_PIN72_BITMASK	(1<<(CORE_PIN72_BIT))
    #define CORE_PIN72_PORTREG	GPIOA_PDOR
    #define CORE_PIN72_PORTSET	GPIOA_PSOR
    #define CORE_PIN72_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN72_DDRREG	GPIOA_PDDR
    #define CORE_PIN72_PINREG	GPIOA_PDIR
    #define CORE_PIN72_CONFIG	PORTA_PCR6
    #define CORE_INT72_PIN		72
    //#define CORE_FTM3_CH0_PIN	72
    
    // PTA7
    #define CORE_PIN73_BIT		7
    #define CORE_PIN73_BITMASK	(1<<(CORE_PIN73_BIT))
    #define CORE_PIN73_PORTREG	GPIOA_PDOR
    #define CORE_PIN73_PORTSET	GPIOA_PSOR
    #define CORE_PIN73_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN73_DDRREG	GPIOA_PDDR
    #define CORE_PIN73_PINREG	GPIOA_PDIR
    #define CORE_PIN73_CONFIG	PORTA_PCR7
    #define CORE_INT73_PIN		73
    //#define CORE_FTM4_CH0_PIN	73
    
    // PTA8
    #define CORE_PIN74_BIT		8
    #define CORE_PIN74_BITMASK	(1<<(CORE_PIN74_BIT))
    #define CORE_PIN74_PORTREG	GPIOA_PDOR
    #define CORE_PIN74_PORTSET	GPIOA_PSOR
    #define CORE_PIN74_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN74_DDRREG	GPIOA_PDDR
    #define CORE_PIN74_PINREG	GPIOA_PDIR
    #define CORE_PIN74_CONFIG	PORTA_PCR8
    #define CORE_INT74_PIN		74
    //#define CORE_FTM0_CH1_PIN	74
    
    // PTE8
    #define CORE_PIN95_BIT		8
    #define CORE_PIN95_BITMASK	(1<<(CORE_PIN95_BIT))
    #define CORE_PIN95_PORTREG	GPIOE_PDOR
    #define CORE_PIN95_PORTSET	GPIOE_PSOR
    #define CORE_PIN95_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN95_DDRREG	GPIOE_PDDR
    #define CORE_PIN95_PINREG	GPIOE_PDIR
    #define CORE_PIN95_CONFIG	PORTE_PCR8
    #define CORE_INT95_PIN		95
    
    // PTE9
    #define CORE_PIN96_BIT		9
    #define CORE_PIN96_BITMASK	(1<<(CORE_PIN96_BIT))
    #define CORE_PIN96_PORTREG	GPIOE_PDOR
    #define CORE_PIN96_PORTSET	GPIOE_PSOR
    #define CORE_PIN96_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN96_DDRREG	GPIOE_PDDR
    #define CORE_PIN96_PINREG	GPIOE_PDIR
    #define CORE_PIN96_CONFIG	PORTE_PCR9
    #define CORE_INT96_PIN		96
    
    // PTE12
    #define CORE_PIN97_BIT		12
    #define CORE_PIN97_BITMASK	(1<<(CORE_PIN97_BIT))
    #define CORE_PIN97_PORTREG	GPIOE_PDOR
    #define CORE_PIN97_PORTSET	GPIOE_PSOR
    #define CORE_PIN97_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN97_DDRREG	GPIOE_PDDR
    #define CORE_PIN97_PINREG	GPIOE_PDIR
    #define CORE_PIN97_CONFIG	PORTE_PCR12
    #define CORE_INT97_PIN		97
    
    // PTE27
    #define CORE_PIN98_BIT		27
    #define CORE_PIN98_BITMASK	(1<<(CORE_PIN98_BIT))
    #define CORE_PIN98_PORTREG	GPIOE_PDOR
    #define CORE_PIN98_PORTSET	GPIOE_PSOR
    #define CORE_PIN98_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN98_DDRREG	GPIOE_PDDR
    #define CORE_PIN98_PINREG	GPIOE_PDIR
    #define CORE_PIN98_CONFIG	PORTE_PCR27
    #define CORE_INT98_PIN		98
    
    // PTE28
    #define CORE_PIN99_BIT		28
    #define CORE_PIN99_BITMASK	(1<<(CORE_PIN99_BIT))
    #define CORE_PIN99_PORTREG	GPIOE_PDOR
    #define CORE_PIN99_PORTSET	GPIOE_PSOR
    #define CORE_PIN99_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN99_DDRREG	GPIOE_PDDR
    #define CORE_PIN99_PINREG	GPIOE_PDIR
    #define CORE_PIN99_CONFIG	PORTE_PCR28
    #define CORE_INT99_PIN		99
    
    
    
    
    //---- End new definitions
    
    
    #define CORE_PIN0_BIT		16
    #define CORE_PIN1_BIT		17
    #define CORE_PIN2_BIT		0
    #define CORE_PIN3_BIT		12
    #define CORE_PIN4_BIT		13
    #define CORE_PIN5_BIT		7
    #define CORE_PIN6_BIT		4
    #define CORE_PIN7_BIT		2
    #define CORE_PIN8_BIT		3
    #define CORE_PIN9_BIT		3
    #define CORE_PIN10_BIT		4
    #define CORE_PIN11_BIT		6
    #define CORE_PIN12_BIT		7
    #define CORE_PIN13_BIT		5
    #define CORE_PIN14_BIT		1
    #define CORE_PIN15_BIT		0
    #define CORE_PIN16_BIT		0
    #define CORE_PIN17_BIT		1
    #define CORE_PIN18_BIT		3
    #define CORE_PIN19_BIT		2
    #define CORE_PIN20_BIT		5
    #define CORE_PIN21_BIT		6
    #define CORE_PIN22_BIT		1
    #define CORE_PIN23_BIT		2
    #define CORE_PIN24_BIT		26
    #define CORE_PIN25_BIT		5
    #define CORE_PIN26_BIT		14
    #define CORE_PIN27_BIT		15
    #define CORE_PIN28_BIT		16
    #define CORE_PIN29_BIT		18
    #define CORE_PIN30_BIT		19
    #define CORE_PIN31_BIT		10
    #define CORE_PIN32_BIT		11
    #define CORE_PIN33_BIT		24
    #define CORE_PIN34_BIT		25
    #define CORE_PIN35_BIT		8
    #define CORE_PIN36_BIT		9
    #define CORE_PIN37_BIT		10
    #define CORE_PIN38_BIT		11
    #define CORE_PIN39_BIT		17
    #define CORE_PIN40_BIT		28
    #define CORE_PIN41_BIT		29
    #define CORE_PIN42_BIT		26
    #define CORE_PIN43_BIT		20
    #define CORE_PIN44_BIT		22
    #define CORE_PIN45_BIT		23
    #define CORE_PIN46_BIT		21
    #define CORE_PIN47_BIT		8
    #define CORE_PIN48_BIT		9
    #define CORE_PIN49_BIT		4
    #define CORE_PIN50_BIT		5
    #define CORE_PIN51_BIT		14
    #define CORE_PIN52_BIT		13
    #define CORE_PIN53_BIT		12
    #define CORE_PIN54_BIT		15
    #define CORE_PIN55_BIT		11
    #define CORE_PIN56_BIT		10
    #define CORE_PIN57_BIT		11
    #define CORE_PIN58_BIT		0
    #define CORE_PIN59_BIT		1
    #define CORE_PIN60_BIT		2
    #define CORE_PIN61_BIT		3
    #define CORE_PIN62_BIT		4
    #define CORE_PIN63_BIT		5
    
    #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))
    #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))
    #define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))
    #define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))
    #define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))
    #define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))
    #define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))
    #define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))
    #define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))
    #define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))
    #define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))
    #define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))
    #define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))
    #define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))
    #define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))
    #define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))
    #define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))
    #define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))
    #define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))
    #define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))
    #define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))
    #define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))
    #define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))
    #define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))
    #define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))
    #define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))
    #define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))
    #define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))
    #define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))
    #define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))
    #define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))
    #define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))
    #define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))
    #define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))
    #define CORE_PIN34_BITMASK	(1<<(CORE_PIN34_BIT))
    #define CORE_PIN35_BITMASK	(1<<(CORE_PIN35_BIT))
    #define CORE_PIN36_BITMASK	(1<<(CORE_PIN36_BIT))
    #define CORE_PIN37_BITMASK	(1<<(CORE_PIN37_BIT))
    #define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))
    #define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))
    #define CORE_PIN40_BITMASK	(1<<(CORE_PIN40_BIT))
    #define CORE_PIN41_BITMASK	(1<<(CORE_PIN41_BIT))
    #define CORE_PIN42_BITMASK	(1<<(CORE_PIN42_BIT))
    #define CORE_PIN43_BITMASK	(1<<(CORE_PIN43_BIT))
    #define CORE_PIN44_BITMASK	(1<<(CORE_PIN44_BIT))
    #define CORE_PIN45_BITMASK	(1<<(CORE_PIN45_BIT))
    #define CORE_PIN46_BITMASK	(1<<(CORE_PIN46_BIT))
    #define CORE_PIN47_BITMASK	(1<<(CORE_PIN47_BIT))
    #define CORE_PIN48_BITMASK	(1<<(CORE_PIN48_BIT))
    #define CORE_PIN49_BITMASK	(1<<(CORE_PIN49_BIT))
    #define CORE_PIN50_BITMASK	(1<<(CORE_PIN50_BIT))
    #define CORE_PIN51_BITMASK	(1<<(CORE_PIN51_BIT))
    #define CORE_PIN52_BITMASK	(1<<(CORE_PIN52_BIT))
    #define CORE_PIN53_BITMASK	(1<<(CORE_PIN53_BIT))
    #define CORE_PIN54_BITMASK	(1<<(CORE_PIN54_BIT))
    #define CORE_PIN55_BITMASK	(1<<(CORE_PIN55_BIT))
    #define CORE_PIN56_BITMASK	(1<<(CORE_PIN56_BIT))
    #define CORE_PIN57_BITMASK	(1<<(CORE_PIN57_BIT))
    #define CORE_PIN58_BITMASK	(1<<(CORE_PIN58_BIT))
    #define CORE_PIN59_BITMASK	(1<<(CORE_PIN59_BIT))
    #define CORE_PIN60_BITMASK	(1<<(CORE_PIN60_BIT))
    #define CORE_PIN61_BITMASK	(1<<(CORE_PIN61_BIT))
    #define CORE_PIN62_BITMASK	(1<<(CORE_PIN62_BIT))
    #define CORE_PIN63_BITMASK	(1<<(CORE_PIN63_BIT))
    
    
    #define CORE_PIN0_PORTREG	GPIOB_PDOR
    #define CORE_PIN1_PORTREG	GPIOB_PDOR
    #define CORE_PIN2_PORTREG	GPIOD_PDOR
    #define CORE_PIN3_PORTREG	GPIOA_PDOR
    #define CORE_PIN4_PORTREG	GPIOA_PDOR
    #define CORE_PIN5_PORTREG	GPIOD_PDOR
    #define CORE_PIN6_PORTREG	GPIOD_PDOR
    #define CORE_PIN7_PORTREG	GPIOD_PDOR
    #define CORE_PIN8_PORTREG	GPIOD_PDOR
    #define CORE_PIN9_PORTREG	GPIOC_PDOR
    #define CORE_PIN10_PORTREG	GPIOC_PDOR
    #define CORE_PIN11_PORTREG	GPIOC_PDOR
    #define CORE_PIN12_PORTREG	GPIOC_PDOR
    #define CORE_PIN13_PORTREG	GPIOC_PDOR
    #define CORE_PIN14_PORTREG	GPIOD_PDOR
    #define CORE_PIN15_PORTREG	GPIOC_PDOR
    #define CORE_PIN16_PORTREG	GPIOB_PDOR
    #define CORE_PIN17_PORTREG	GPIOB_PDOR
    #define CORE_PIN18_PORTREG	GPIOB_PDOR
    #define CORE_PIN19_PORTREG	GPIOB_PDOR
    #define CORE_PIN20_PORTREG	GPIOD_PDOR
    #define CORE_PIN21_PORTREG	GPIOD_PDOR
    #define CORE_PIN22_PORTREG	GPIOC_PDOR
    #define CORE_PIN23_PORTREG	GPIOC_PDOR
    #define CORE_PIN24_PORTREG	GPIOE_PDOR
    #define CORE_PIN25_PORTREG	GPIOA_PDOR
    #define CORE_PIN26_PORTREG	GPIOA_PDOR
    #define CORE_PIN27_PORTREG	GPIOA_PDOR
    #define CORE_PIN28_PORTREG	GPIOA_PDOR
    #define CORE_PIN29_PORTREG	GPIOB_PDOR
    #define CORE_PIN30_PORTREG	GPIOB_PDOR
    #define CORE_PIN31_PORTREG	GPIOB_PDOR
    #define CORE_PIN32_PORTREG	GPIOB_PDOR
    #define CORE_PIN33_PORTREG	GPIOE_PDOR
    #define CORE_PIN34_PORTREG	GPIOE_PDOR
    #define CORE_PIN35_PORTREG	GPIOC_PDOR
    #define CORE_PIN36_PORTREG	GPIOC_PDOR
    #define CORE_PIN37_PORTREG	GPIOC_PDOR
    #define CORE_PIN38_PORTREG	GPIOC_PDOR
    #define CORE_PIN39_PORTREG	GPIOA_PDOR
    #define CORE_PIN40_PORTREG	GPIOA_PDOR
    #define CORE_PIN41_PORTREG	GPIOA_PDOR
    #define CORE_PIN42_PORTREG	GPIOA_PDOR
    #define CORE_PIN43_PORTREG	GPIOB_PDOR
    #define CORE_PIN44_PORTREG	GPIOB_PDOR
    #define CORE_PIN45_PORTREG	GPIOB_PDOR
    #define CORE_PIN46_PORTREG	GPIOB_PDOR
    #define CORE_PIN47_PORTREG	GPIOD_PDOR
    #define CORE_PIN48_PORTREG	GPIOD_PDOR
    #define CORE_PIN49_PORTREG	GPIOB_PDOR
    #define CORE_PIN50_PORTREG	GPIOB_PDOR
    #define CORE_PIN51_PORTREG	GPIOD_PDOR
    #define CORE_PIN52_PORTREG	GPIOD_PDOR
    #define CORE_PIN53_PORTREG	GPIOD_PDOR
    #define CORE_PIN54_PORTREG	GPIOD_PDOR
    #define CORE_PIN55_PORTREG	GPIOD_PDOR
    #define CORE_PIN56_PORTREG	GPIOE_PDOR
    #define CORE_PIN57_PORTREG	GPIOE_PDOR
    #define CORE_PIN58_PORTREG	GPIOE_PDOR
    #define CORE_PIN59_PORTREG	GPIOE_PDOR
    #define CORE_PIN60_PORTREG	GPIOE_PDOR
    #define CORE_PIN61_PORTREG	GPIOE_PDOR
    #define CORE_PIN62_PORTREG	GPIOE_PDOR
    #define CORE_PIN63_PORTREG	GPIOE_PDOR
    
    #define CORE_PIN0_PORTSET	GPIOB_PSOR
    #define CORE_PIN1_PORTSET	GPIOB_PSOR
    #define CORE_PIN2_PORTSET	GPIOD_PSOR
    #define CORE_PIN3_PORTSET	GPIOA_PSOR
    #define CORE_PIN4_PORTSET	GPIOA_PSOR
    #define CORE_PIN5_PORTSET	GPIOD_PSOR
    #define CORE_PIN6_PORTSET	GPIOD_PSOR
    #define CORE_PIN7_PORTSET	GPIOD_PSOR
    #define CORE_PIN8_PORTSET	GPIOD_PSOR
    #define CORE_PIN9_PORTSET	GPIOC_PSOR
    #define CORE_PIN10_PORTSET	GPIOC_PSOR
    #define CORE_PIN11_PORTSET	GPIOC_PSOR
    #define CORE_PIN12_PORTSET	GPIOC_PSOR
    #define CORE_PIN13_PORTSET	GPIOC_PSOR
    #define CORE_PIN14_PORTSET	GPIOD_PSOR
    #define CORE_PIN15_PORTSET	GPIOC_PSOR
    #define CORE_PIN16_PORTSET	GPIOB_PSOR
    #define CORE_PIN17_PORTSET	GPIOB_PSOR
    #define CORE_PIN18_PORTSET	GPIOB_PSOR
    #define CORE_PIN19_PORTSET	GPIOB_PSOR
    #define CORE_PIN20_PORTSET	GPIOD_PSOR
    #define CORE_PIN21_PORTSET	GPIOD_PSOR
    #define CORE_PIN22_PORTSET	GPIOC_PSOR
    #define CORE_PIN23_PORTSET	GPIOC_PSOR
    #define CORE_PIN24_PORTSET	GPIOE_PSOR
    #define CORE_PIN25_PORTSET	GPIOA_PSOR
    #define CORE_PIN26_PORTSET	GPIOA_PSOR
    #define CORE_PIN27_PORTSET	GPIOA_PSOR
    #define CORE_PIN28_PORTSET	GPIOA_PSOR
    #define CORE_PIN29_PORTSET	GPIOB_PSOR
    #define CORE_PIN30_PORTSET	GPIOB_PSOR
    #define CORE_PIN31_PORTSET	GPIOB_PSOR
    #define CORE_PIN32_PORTSET	GPIOB_PSOR
    #define CORE_PIN33_PORTSET	GPIOE_PSOR
    #define CORE_PIN34_PORTSET	GPIOE_PSOR
    #define CORE_PIN35_PORTSET	GPIOC_PSOR
    #define CORE_PIN36_PORTSET	GPIOC_PSOR
    #define CORE_PIN37_PORTSET	GPIOC_PSOR
    #define CORE_PIN38_PORTSET	GPIOC_PSOR
    #define CORE_PIN39_PORTSET	GPIOA_PSOR
    #define CORE_PIN40_PORTSET	GPIOA_PSOR
    #define CORE_PIN41_PORTSET	GPIOA_PSOR
    #define CORE_PIN42_PORTSET	GPIOA_PSOR
    #define CORE_PIN43_PORTSET	GPIOB_PSOR
    #define CORE_PIN44_PORTSET	GPIOB_PSOR
    #define CORE_PIN45_PORTSET	GPIOB_PSOR
    #define CORE_PIN46_PORTSET	GPIOB_PSOR
    #define CORE_PIN47_PORTSET	GPIOD_PSOR
    #define CORE_PIN48_PORTSET	GPIOD_PSOR
    #define CORE_PIN49_PORTSET	GPIOB_PSOR
    #define CORE_PIN50_PORTSET	GPIOB_PSOR
    #define CORE_PIN51_PORTSET	GPIOD_PSOR
    #define CORE_PIN52_PORTSET	GPIOD_PSOR
    #define CORE_PIN53_PORTSET	GPIOD_PSOR
    #define CORE_PIN54_PORTSET	GPIOD_PSOR
    #define CORE_PIN55_PORTSET	GPIOD_PSOR
    #define CORE_PIN56_PORTSET	GPIOE_PSOR
    #define CORE_PIN57_PORTSET	GPIOE_PSOR
    #define CORE_PIN58_PORTSET	GPIOE_PSOR
    #define CORE_PIN59_PORTSET	GPIOE_PSOR
    #define CORE_PIN60_PORTSET	GPIOE_PSOR
    #define CORE_PIN61_PORTSET	GPIOE_PSOR
    #define CORE_PIN62_PORTSET	GPIOE_PSOR
    #define CORE_PIN63_PORTSET	GPIOE_PSOR
    
    #define CORE_PIN0_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN1_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN2_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN3_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN4_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN5_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN6_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN7_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN8_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN9_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN10_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN11_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN12_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN13_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN14_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN15_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN16_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN17_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN18_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN19_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN20_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN21_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN22_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN23_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN24_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN25_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN26_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN27_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN28_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN29_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN30_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN31_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN32_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN33_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN34_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN35_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN36_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN37_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN38_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN39_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN40_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN41_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN42_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN43_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN44_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN45_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN46_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN47_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN48_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN49_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN50_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN51_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN52_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN53_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN54_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN55_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN56_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN57_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN58_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN59_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN60_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN61_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN62_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN63_PORTCLEAR	GPIOE_PCOR
    
    #define CORE_PIN0_DDRREG	GPIOB_PDDR
    #define CORE_PIN1_DDRREG	GPIOB_PDDR
    #define CORE_PIN2_DDRREG	GPIOD_PDDR
    #define CORE_PIN3_DDRREG	GPIOA_PDDR
    #define CORE_PIN4_DDRREG	GPIOA_PDDR
    #define CORE_PIN5_DDRREG	GPIOD_PDDR
    #define CORE_PIN6_DDRREG	GPIOD_PDDR
    #define CORE_PIN7_DDRREG	GPIOD_PDDR
    #define CORE_PIN8_DDRREG	GPIOD_PDDR
    #define CORE_PIN9_DDRREG	GPIOC_PDDR
    #define CORE_PIN10_DDRREG	GPIOC_PDDR
    #define CORE_PIN11_DDRREG	GPIOC_PDDR
    #define CORE_PIN12_DDRREG	GPIOC_PDDR
    #define CORE_PIN13_DDRREG	GPIOC_PDDR
    #define CORE_PIN14_DDRREG	GPIOD_PDDR
    #define CORE_PIN15_DDRREG	GPIOC_PDDR
    #define CORE_PIN16_DDRREG	GPIOB_PDDR
    #define CORE_PIN17_DDRREG	GPIOB_PDDR
    #define CORE_PIN18_DDRREG	GPIOB_PDDR
    #define CORE_PIN19_DDRREG	GPIOB_PDDR
    #define CORE_PIN20_DDRREG	GPIOD_PDDR
    #define CORE_PIN21_DDRREG	GPIOD_PDDR
    #define CORE_PIN22_DDRREG	GPIOC_PDDR
    #define CORE_PIN23_DDRREG	GPIOC_PDDR
    #define CORE_PIN24_DDRREG	GPIOE_PDDR
    #define CORE_PIN25_DDRREG	GPIOA_PDDR
    #define CORE_PIN26_DDRREG	GPIOA_PDDR
    #define CORE_PIN27_DDRREG	GPIOA_PDDR
    #define CORE_PIN28_DDRREG	GPIOA_PDDR
    #define CORE_PIN29_DDRREG	GPIOB_PDDR
    #define CORE_PIN30_DDRREG	GPIOB_PDDR
    #define CORE_PIN31_DDRREG	GPIOB_PDDR
    #define CORE_PIN32_DDRREG	GPIOB_PDDR
    #define CORE_PIN33_DDRREG	GPIOE_PDDR
    #define CORE_PIN34_DDRREG	GPIOE_PDDR
    #define CORE_PIN35_DDRREG	GPIOC_PDDR
    #define CORE_PIN36_DDRREG	GPIOC_PDDR
    #define CORE_PIN37_DDRREG	GPIOC_PDDR
    #define CORE_PIN38_DDRREG	GPIOC_PDDR
    #define CORE_PIN39_DDRREG	GPIOA_PDDR
    #define CORE_PIN40_DDRREG	GPIOA_PDDR
    #define CORE_PIN41_DDRREG	GPIOA_PDDR
    #define CORE_PIN42_DDRREG	GPIOA_PDDR
    #define CORE_PIN43_DDRREG	GPIOB_PDDR
    #define CORE_PIN44_DDRREG	GPIOB_PDDR
    #define CORE_PIN45_DDRREG	GPIOB_PDDR
    #define CORE_PIN46_DDRREG	GPIOB_PDDR
    #define CORE_PIN47_DDRREG	GPIOD_PDDR
    #define CORE_PIN48_DDRREG	GPIOD_PDDR
    #define CORE_PIN49_DDRREG	GPIOB_PDDR
    #define CORE_PIN50_DDRREG	GPIOB_PDDR
    #define CORE_PIN51_DDRREG	GPIOD_PDDR
    #define CORE_PIN52_DDRREG	GPIOD_PDDR
    #define CORE_PIN53_DDRREG	GPIOD_PDDR
    #define CORE_PIN54_DDRREG	GPIOD_PDDR
    #define CORE_PIN55_DDRREG	GPIOD_PDDR
    #define CORE_PIN56_DDRREG	GPIOE_PDDR
    #define CORE_PIN57_DDRREG	GPIOE_PDDR
    #define CORE_PIN58_DDRREG	GPIOE_PDDR
    #define CORE_PIN59_DDRREG	GPIOE_PDDR
    #define CORE_PIN60_DDRREG	GPIOE_PDDR
    #define CORE_PIN61_DDRREG	GPIOE_PDDR
    #define CORE_PIN62_DDRREG	GPIOE_PDDR
    #define CORE_PIN63_DDRREG	GPIOE_PDDR
    
    #define CORE_PIN0_PINREG	GPIOB_PDIR
    #define CORE_PIN1_PINREG	GPIOB_PDIR
    #define CORE_PIN2_PINREG	GPIOD_PDIR
    #define CORE_PIN3_PINREG	GPIOA_PDIR
    #define CORE_PIN4_PINREG	GPIOA_PDIR
    #define CORE_PIN5_PINREG	GPIOD_PDIR
    #define CORE_PIN6_PINREG	GPIOD_PDIR
    #define CORE_PIN7_PINREG	GPIOD_PDIR
    #define CORE_PIN8_PINREG	GPIOD_PDIR
    #define CORE_PIN9_PINREG	GPIOC_PDIR
    #define CORE_PIN10_PINREG	GPIOC_PDIR
    #define CORE_PIN11_PINREG	GPIOC_PDIR
    #define CORE_PIN12_PINREG	GPIOC_PDIR
    #define CORE_PIN13_PINREG	GPIOC_PDIR
    #define CORE_PIN14_PINREG	GPIOD_PDIR
    #define CORE_PIN15_PINREG	GPIOC_PDIR
    #define CORE_PIN16_PINREG	GPIOB_PDIR
    #define CORE_PIN17_PINREG	GPIOB_PDIR
    #define CORE_PIN18_PINREG	GPIOB_PDIR
    #define CORE_PIN19_PINREG	GPIOB_PDIR
    #define CORE_PIN20_PINREG	GPIOD_PDIR
    #define CORE_PIN21_PINREG	GPIOD_PDIR
    #define CORE_PIN22_PINREG	GPIOC_PDIR
    #define CORE_PIN23_PINREG	GPIOC_PDIR
    #define CORE_PIN24_PINREG	GPIOE_PDIR
    #define CORE_PIN25_PINREG	GPIOA_PDIR
    #define CORE_PIN26_PINREG	GPIOA_PDIR
    #define CORE_PIN27_PINREG	GPIOA_PDIR
    #define CORE_PIN28_PINREG	GPIOA_PDIR
    #define CORE_PIN29_PINREG	GPIOB_PDIR
    #define CORE_PIN30_PINREG	GPIOB_PDIR
    #define CORE_PIN31_PINREG	GPIOB_PDIR
    #define CORE_PIN32_PINREG	GPIOB_PDIR
    #define CORE_PIN33_PINREG	GPIOE_PDIR
    #define CORE_PIN34_PINREG	GPIOE_PDIR
    #define CORE_PIN35_PINREG	GPIOC_PDIR
    #define CORE_PIN36_PINREG	GPIOC_PDIR
    #define CORE_PIN37_PINREG	GPIOC_PDIR
    #define CORE_PIN38_PINREG	GPIOC_PDIR
    #define CORE_PIN39_PINREG	GPIOA_PDIR
    #define CORE_PIN40_PINREG	GPIOA_PDIR
    #define CORE_PIN41_PINREG	GPIOA_PDIR
    #define CORE_PIN42_PINREG	GPIOA_PDIR
    #define CORE_PIN43_PINREG	GPIOB_PDIR
    #define CORE_PIN44_PINREG	GPIOB_PDIR
    #define CORE_PIN45_PINREG	GPIOB_PDIR
    #define CORE_PIN46_PINREG	GPIOB_PDIR
    #define CORE_PIN47_PINREG	GPIOD_PDIR
    #define CORE_PIN48_PINREG	GPIOD_PDIR
    #define CORE_PIN49_PINREG	GPIOB_PDIR
    #define CORE_PIN50_PINREG	GPIOB_PDIR
    #define CORE_PIN51_PINREG	GPIOD_PDIR
    #define CORE_PIN52_PINREG	GPIOD_PDIR
    #define CORE_PIN53_PINREG	GPIOD_PDIR
    #define CORE_PIN54_PINREG	GPIOD_PDIR
    #define CORE_PIN55_PINREG	GPIOD_PDIR
    #define CORE_PIN56_PINREG	GPIOE_PDIR
    #define CORE_PIN57_PINREG	GPIOE_PDIR
    #define CORE_PIN58_PINREG	GPIOE_PDIR
    #define CORE_PIN59_PINREG	GPIOE_PDIR
    #define CORE_PIN60_PINREG	GPIOE_PDIR
    #define CORE_PIN61_PINREG	GPIOE_PDIR
    #define CORE_PIN62_PINREG	GPIOE_PDIR
    #define CORE_PIN63_PINREG	GPIOE_PDIR
    
    #define CORE_PIN0_CONFIG	PORTB_PCR16
    #define CORE_PIN1_CONFIG	PORTB_PCR17
    #define CORE_PIN2_CONFIG	PORTD_PCR0
    #define CORE_PIN3_CONFIG	PORTA_PCR12
    #define CORE_PIN4_CONFIG	PORTA_PCR13
    #define CORE_PIN5_CONFIG	PORTD_PCR7
    #define CORE_PIN6_CONFIG	PORTD_PCR4
    #define CORE_PIN7_CONFIG	PORTD_PCR2
    #define CORE_PIN8_CONFIG	PORTD_PCR3
    #define CORE_PIN9_CONFIG	PORTC_PCR3
    #define CORE_PIN10_CONFIG	PORTC_PCR4
    #define CORE_PIN11_CONFIG	PORTC_PCR6
    #define CORE_PIN12_CONFIG	PORTC_PCR7
    #define CORE_PIN13_CONFIG	PORTC_PCR5
    #define CORE_PIN14_CONFIG	PORTD_PCR1
    #define CORE_PIN15_CONFIG	PORTC_PCR0
    #define CORE_PIN16_CONFIG	PORTB_PCR0
    #define CORE_PIN17_CONFIG	PORTB_PCR1
    #define CORE_PIN18_CONFIG	PORTB_PCR3
    #define CORE_PIN19_CONFIG	PORTB_PCR2
    #define CORE_PIN20_CONFIG	PORTD_PCR5
    #define CORE_PIN21_CONFIG	PORTD_PCR6
    #define CORE_PIN22_CONFIG	PORTC_PCR1
    #define CORE_PIN23_CONFIG	PORTC_PCR2
    #define CORE_PIN24_CONFIG	PORTE_PCR26
    #define CORE_PIN25_CONFIG	PORTA_PCR5
    #define CORE_PIN26_CONFIG	PORTA_PCR14
    #define CORE_PIN27_CONFIG	PORTA_PCR15
    #define CORE_PIN28_CONFIG	PORTA_PCR16
    #define CORE_PIN29_CONFIG	PORTB_PCR18
    #define CORE_PIN30_CONFIG	PORTB_PCR19
    #define CORE_PIN31_CONFIG	PORTB_PCR10
    #define CORE_PIN32_CONFIG	PORTB_PCR11
    #define CORE_PIN33_CONFIG	PORTE_PCR24
    #define CORE_PIN34_CONFIG	PORTE_PCR25
    #define CORE_PIN35_CONFIG	PORTC_PCR8
    #define CORE_PIN36_CONFIG	PORTC_PCR9
    #define CORE_PIN37_CONFIG	PORTC_PCR10
    #define CORE_PIN38_CONFIG	PORTC_PCR11
    #define CORE_PIN39_CONFIG	PORTA_PCR17
    #define CORE_PIN40_CONFIG	PORTA_PCR28
    #define CORE_PIN41_CONFIG	PORTA_PCR29
    #define CORE_PIN42_CONFIG	PORTA_PCR26
    #define CORE_PIN43_CONFIG	PORTB_PCR20
    #define CORE_PIN44_CONFIG	PORTB_PCR22
    #define CORE_PIN45_CONFIG	PORTB_PCR23
    #define CORE_PIN46_CONFIG	PORTB_PCR21
    #define CORE_PIN47_CONFIG	PORTD_PCR8
    #define CORE_PIN48_CONFIG	PORTD_PCR9
    #define CORE_PIN49_CONFIG	PORTB_PCR4
    #define CORE_PIN50_CONFIG	PORTB_PCR5
    #define CORE_PIN51_CONFIG	PORTD_PCR14
    #define CORE_PIN52_CONFIG	PORTD_PCR13
    #define CORE_PIN53_CONFIG	PORTD_PCR12
    #define CORE_PIN54_CONFIG	PORTD_PCR15
    #define CORE_PIN55_CONFIG	PORTD_PCR11
    #define CORE_PIN56_CONFIG	PORTE_PCR10
    #define CORE_PIN57_CONFIG	PORTE_PCR11
    #define CORE_PIN58_CONFIG	PORTE_PCR0
    #define CORE_PIN59_CONFIG	PORTE_PCR1
    #define CORE_PIN60_CONFIG	PORTE_PCR2
    #define CORE_PIN61_CONFIG	PORTE_PCR3
    #define CORE_PIN62_CONFIG	PORTE_PCR4
    #define CORE_PIN63_CONFIG	PORTE_PCR5
    
    #define CORE_ADC0_PIN		14
    #define CORE_ADC1_PIN		15
    #define CORE_ADC2_PIN		16
    #define CORE_ADC3_PIN		17
    #define CORE_ADC4_PIN		18
    #define CORE_ADC5_PIN		19
    #define CORE_ADC6_PIN		20
    #define CORE_ADC7_PIN		21
    #define CORE_ADC8_PIN		22
    #define CORE_ADC9_PIN		23
    #define CORE_ADC10_PIN		64
    #define CORE_ADC11_PIN		65
    #define CORE_ADC12_PIN		31
    #define CORE_ADC13_PIN		32
    #define CORE_ADC14_PIN		33
    #define CORE_ADC15_PIN		34
    #define CORE_ADC16_PIN		35
    #define CORE_ADC17_PIN		36
    #define CORE_ADC18_PIN		37
    #define CORE_ADC19_PIN		38
    #define CORE_ADC20_PIN		39
    #define CORE_ADC21_PIN		66
    #define CORE_ADC22_PIN		67
    #define CORE_ADC23_PIN		49
    #define CORE_ADC24_PIN		50
    #define CORE_ADC25_PIN		68
    #define CORE_ADC26_PIN		69
    
    #define CORE_RXD0_PIN		0
    #define CORE_TXD0_PIN		1
    #define CORE_RXD1_PIN		9
    #define CORE_TXD1_PIN		10
    #define CORE_RXD2_PIN		7
    #define CORE_TXD2_PIN		8
    #define CORE_RXD3_PIN		31
    #define CORE_TXD3_PIN		32
    #define CORE_RXD4_PIN		34
    #define CORE_TXD4_PIN		33
    
    #define CORE_INT0_PIN		0
    #define CORE_INT1_PIN		1
    #define CORE_INT2_PIN		2
    #define CORE_INT3_PIN		3
    #define CORE_INT4_PIN		4
    #define CORE_INT5_PIN		5
    #define CORE_INT6_PIN		6
    #define CORE_INT7_PIN		7
    #define CORE_INT8_PIN		8
    #define CORE_INT9_PIN		9
    #define CORE_INT10_PIN		10
    #define CORE_INT11_PIN		11
    #define CORE_INT12_PIN		12
    #define CORE_INT13_PIN		13
    #define CORE_INT14_PIN		14
    #define CORE_INT15_PIN		15
    #define CORE_INT16_PIN		16
    #define CORE_INT17_PIN		17
    #define CORE_INT18_PIN		18
    #define CORE_INT19_PIN		19
    #define CORE_INT20_PIN		20
    #define CORE_INT21_PIN		21
    #define CORE_INT22_PIN		22
    #define CORE_INT23_PIN		23
    #define CORE_INT24_PIN		24
    #define CORE_INT25_PIN		25
    #define CORE_INT26_PIN		26
    #define CORE_INT27_PIN		27
    #define CORE_INT28_PIN		28
    #define CORE_INT29_PIN		29
    #define CORE_INT30_PIN		30
    #define CORE_INT31_PIN		31
    #define CORE_INT32_PIN		32
    #define CORE_INT33_PIN		33
    #define CORE_INT34_PIN		34
    #define CORE_INT35_PIN		35
    #define CORE_INT36_PIN		36
    #define CORE_INT37_PIN		37
    #define CORE_INT38_PIN		38
    #define CORE_INT39_PIN		39
    #define CORE_INT40_PIN		40
    #define CORE_INT41_PIN		41
    #define CORE_INT42_PIN		42
    #define CORE_INT43_PIN		43
    #define CORE_INT44_PIN		44
    #define CORE_INT45_PIN		45
    #define CORE_INT46_PIN		46
    #define CORE_INT47_PIN		47
    #define CORE_INT48_PIN		48
    #define CORE_INT49_PIN		49
    #define CORE_INT50_PIN		50
    #define CORE_INT51_PIN		51
    #define CORE_INT52_PIN		52
    #define CORE_INT53_PIN		53
    #define CORE_INT54_PIN		54
    #define CORE_INT55_PIN		55
    #define CORE_INT56_PIN		56
    #define CORE_INT57_PIN		57
    #define CORE_INT58_PIN		58
    #define CORE_INT59_PIN		59
    #define CORE_INT60_PIN		60
    #define CORE_INT61_PIN		61
    #define CORE_INT62_PIN		62
    #define CORE_INT63_PIN		63
    #define CORE_INT_EVERY_PIN	1
    
    
    
    
    
    #define CORE_FTM0_CH0_PIN	22
    #define CORE_FTM0_CH1_PIN	23
    #define CORE_FTM0_CH2_PIN	 9
    #define CORE_FTM0_CH3_PIN	10
    #define CORE_FTM0_CH4_PIN	 6
    #define CORE_FTM0_CH5_PIN	20
    #define CORE_FTM0_CH6_PIN	21
    #define CORE_FTM0_CH7_PIN	 5
    #define CORE_FTM1_CH0_PIN	 3
    #define CORE_FTM1_CH1_PIN	 4
    #define CORE_FTM2_CH0_PIN	29
    #define CORE_FTM2_CH1_PIN	30
    #define CORE_FTM3_CH0_PIN	 2
    #define CORE_FTM3_CH1_PIN	14
    #define CORE_FTM3_CH2_PIN	 7
    #define CORE_FTM3_CH3_PIN	 8
    #define CORE_FTM3_CH4_PIN	35
    #define CORE_FTM3_CH5_PIN	36
    #define CORE_FTM3_CH6_PIN	37
    #define CORE_FTM3_CH7_PIN	38
    #define CORE_TPM1_CH0_PIN	16
    #define CORE_TPM1_CH1_PIN	17
    
    
    
    #ifdef __cplusplus
    extern "C" {
    #endif
    
    void digitalWrite(uint8_t pin, uint8_t val);
    static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused));
    static inline void digitalWriteFast(uint8_t pin, uint8_t val)
    {
    	if (__builtin_constant_p(pin)) {
    		if (val) {
    			if (pin == 0) {
    				CORE_PIN0_PORTSET = CORE_PIN0_BITMASK;
    			} else if (pin == 1) {
    				CORE_PIN1_PORTSET = CORE_PIN1_BITMASK;
    			} else if (pin == 2) {
    				CORE_PIN2_PORTSET = CORE_PIN2_BITMASK;
    			} else if (pin == 3) {
    				CORE_PIN3_PORTSET = CORE_PIN3_BITMASK;
    			} else if (pin == 4) {
    				CORE_PIN4_PORTSET = CORE_PIN4_BITMASK;
    			} else if (pin == 5) {
    				CORE_PIN5_PORTSET = CORE_PIN5_BITMASK;
    			} else if (pin == 6) {
    				CORE_PIN6_PORTSET = CORE_PIN6_BITMASK;
    			} else if (pin == 7) {
    				CORE_PIN7_PORTSET = CORE_PIN7_BITMASK;
    			} else if (pin == 8) {
    				CORE_PIN8_PORTSET = CORE_PIN8_BITMASK;
    			} else if (pin == 9) {
    				CORE_PIN9_PORTSET = CORE_PIN9_BITMASK;
    			} else if (pin == 10) {
    				CORE_PIN10_PORTSET = CORE_PIN10_BITMASK;
    			} else if (pin == 11) {
    				CORE_PIN11_PORTSET = CORE_PIN11_BITMASK;
    			} else if (pin == 12) {
    				CORE_PIN12_PORTSET = CORE_PIN12_BITMASK;
    			} else if (pin == 13) {
    				CORE_PIN13_PORTSET = CORE_PIN13_BITMASK;
    			} else if (pin == 14) {
    				CORE_PIN14_PORTSET = CORE_PIN14_BITMASK;
    			} else if (pin == 15) {
    				CORE_PIN15_PORTSET = CORE_PIN15_BITMASK;
    			} else if (pin == 16) {
    				CORE_PIN16_PORTSET = CORE_PIN16_BITMASK;
    			} else if (pin == 17) {
    				CORE_PIN17_PORTSET = CORE_PIN17_BITMASK;
    			} else if (pin == 18) {
    				CORE_PIN18_PORTSET = CORE_PIN18_BITMASK;
    			} else if (pin == 19) {
    				CORE_PIN19_PORTSET = CORE_PIN19_BITMASK;
    			} else if (pin == 20) {
    				CORE_PIN20_PORTSET = CORE_PIN20_BITMASK;
    			} else if (pin == 21) {
    				CORE_PIN21_PORTSET = CORE_PIN21_BITMASK;
    			} else if (pin == 22) {
    				CORE_PIN22_PORTSET = CORE_PIN22_BITMASK;
    			} else if (pin == 23) {
    				CORE_PIN23_PORTSET = CORE_PIN23_BITMASK;
    			} else if (pin == 24) {
    				CORE_PIN24_PORTSET = CORE_PIN24_BITMASK;
    			} else if (pin == 25) {
    				CORE_PIN25_PORTSET = CORE_PIN25_BITMASK;
    			} else if (pin == 26) {
    				CORE_PIN26_PORTSET = CORE_PIN26_BITMASK;
    			}
    			#if defined(CORE_PIN27_PORTSET)
    			  else if (pin == 27) {
    				CORE_PIN27_PORTSET = CORE_PIN27_BITMASK;
    			} else if (pin == 28) {
    				CORE_PIN28_PORTSET = CORE_PIN28_BITMASK;
    			} else if (pin == 29) {
    				CORE_PIN29_PORTSET = CORE_PIN29_BITMASK;
    			} else if (pin == 30) {
    				CORE_PIN30_PORTSET = CORE_PIN30_BITMASK;
    			} else if (pin == 31) {
    				CORE_PIN31_PORTSET = CORE_PIN31_BITMASK;
    			} else if (pin == 32) {
    				CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;
    			} else if (pin == 33) {
    				CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;
    			}
    			#endif
    			#if defined(CORE_PIN34_PORTSET)
    			  else if (pin == 34) {
    				CORE_PIN34_PORTSET = CORE_PIN34_BITMASK;
    			} else if (pin == 35) {
    				CORE_PIN35_PORTSET = CORE_PIN35_BITMASK;
    			} else if (pin == 36) {
    				CORE_PIN36_PORTSET = CORE_PIN36_BITMASK;
    			} else if (pin == 37) {
    				CORE_PIN37_PORTSET = CORE_PIN37_BITMASK;
    			} else if (pin == 38) {
    				CORE_PIN38_PORTSET = CORE_PIN38_BITMASK;
    			} else if (pin == 39) {
    				CORE_PIN39_PORTSET = CORE_PIN39_BITMASK;
    			} else if (pin == 40) {
    				CORE_PIN40_PORTSET = CORE_PIN40_BITMASK;
    			} else if (pin == 41) {
    				CORE_PIN41_PORTSET = CORE_PIN41_BITMASK;
    			} else if (pin == 42) {
    				CORE_PIN42_PORTSET = CORE_PIN42_BITMASK;
    			} else if (pin == 43) {
    				CORE_PIN43_PORTSET = CORE_PIN43_BITMASK;
    			} else if (pin == 44) {
    				CORE_PIN44_PORTSET = CORE_PIN44_BITMASK;
    			} else if (pin == 45) {
    				CORE_PIN45_PORTSET = CORE_PIN45_BITMASK;
    			} else if (pin == 46) {
    				CORE_PIN46_PORTSET = CORE_PIN46_BITMASK;
    			} else if (pin == 47) {
    				CORE_PIN47_PORTSET = CORE_PIN47_BITMASK;
    			} else if (pin == 48) {
    				CORE_PIN48_PORTSET = CORE_PIN48_BITMASK;
    			} else if (pin == 49) {
    				CORE_PIN49_PORTSET = CORE_PIN49_BITMASK;
    			} else if (pin == 50) {
    				CORE_PIN50_PORTSET = CORE_PIN50_BITMASK;
    			} else if (pin == 51) {
    				CORE_PIN51_PORTSET = CORE_PIN51_BITMASK;
    			} else if (pin == 52) {
    				CORE_PIN52_PORTSET = CORE_PIN52_BITMASK;
    			} else if (pin == 53) {
    				CORE_PIN53_PORTSET = CORE_PIN53_BITMASK;
    			} else if (pin == 54) {
    				CORE_PIN54_PORTSET = CORE_PIN54_BITMASK;
    			} else if (pin == 55) {
    				CORE_PIN55_PORTSET = CORE_PIN55_BITMASK;
    			} else if (pin == 56) {
    				CORE_PIN56_PORTSET = CORE_PIN56_BITMASK;
    			} else if (pin == 57) {
    				CORE_PIN57_PORTSET = CORE_PIN57_BITMASK;
    			} else if (pin == 58) {
    				CORE_PIN58_PORTSET = CORE_PIN58_BITMASK;
    			} else if (pin == 59) {
    				CORE_PIN59_PORTSET = CORE_PIN59_BITMASK;
    			} else if (pin == 60) {
    				CORE_PIN60_PORTSET = CORE_PIN60_BITMASK;
    			} else if (pin == 61) {
    				CORE_PIN61_PORTSET = CORE_PIN61_BITMASK;
    			} else if (pin == 62) {
    				CORE_PIN62_PORTSET = CORE_PIN62_BITMASK;
    			} else if (pin == 63) {
    				CORE_PIN63_PORTSET = CORE_PIN63_BITMASK;
    			} else if (pin == 72) {
    				CORE_PIN72_PORTSET = CORE_PIN72_BITMASK;
    			} else if (pin == 73) {
    				CORE_PIN73_PORTSET = CORE_PIN73_BITMASK;
    			} else if (pin == 74) {
    				CORE_PIN74_PORTSET = CORE_PIN74_BITMASK;
    			} else if (pin == 95) {
    				CORE_PIN95_PORTSET = CORE_PIN95_BITMASK;
    			} else if (pin == 96) {
    				CORE_PIN96_PORTSET = CORE_PIN96_BITMASK;
    			} else if (pin == 97) {
    				CORE_PIN97_PORTSET = CORE_PIN97_BITMASK;
    			} else if (pin == 98) {
    				CORE_PIN98_PORTSET = CORE_PIN98_BITMASK;
    			} else if (pin == 99) {
    				CORE_PIN99_PORTSET = CORE_PIN99_BITMASK;
    			}
    			#endif
    		} else {
    			if (pin == 0) {
    				CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;
    			} else if (pin == 1) {
    				CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK;
    			} else if (pin == 2) {
    				CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK;
    			} else if (pin == 3) {
    				CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK;
    			} else if (pin == 4) {
    				CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK;
    			} else if (pin == 5) {
    				CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK;
    			} else if (pin == 6) {
    				CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK;
    			} else if (pin == 7) {
    				CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK;
    			} else if (pin == 8) {
    				CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK;
    			} else if (pin == 9) {
    				CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK;
    			} else if (pin == 10) {
    				CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK;
    			} else if (pin == 11) {
    				CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK;
    			} else if (pin == 12) {
    				CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK;
    			} else if (pin == 13) {
    				CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK;
    			} else if (pin == 14) {
    				CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK;
    			} else if (pin == 15) {
    				CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK;
    			} else if (pin == 16) {
    				CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK;
    			} else if (pin == 17) {
    				CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK;
    			} else if (pin == 18) {
    				CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK;
    			} else if (pin == 19) {
    				CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK;
    			} else if (pin == 20) {
    				CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK;
    			} else if (pin == 21) {
    				CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK;
    			} else if (pin == 22) {
    				CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK;
    			} else if (pin == 23) {
    				CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK;
    			} else if (pin == 24) {
    				CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK;
    			} else if (pin == 25) {
    				CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK;
    			} else if (pin == 26) {
    				CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK;
    			}
    			#if defined(CORE_PIN27_PORTCLEAR)
    			  else if (pin == 27) {
    				CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK;
    			} else if (pin == 28) {
    				CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK;
    			} else if (pin == 29) {
    				CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK;
    			} else if (pin == 30) {
    				CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK;
    			} else if (pin == 31) {
    				CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK;
    			} else if (pin == 32) {
    				CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;
    			} else if (pin == 33) {
    				CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;
    			}
    			#endif
    			#if defined(CORE_PIN34_PORTCLEAR)
    			  else if (pin == 34) {
    				CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK;
    			} else if (pin == 35) {
    				CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK;
    			} else if (pin == 36) {
    				CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK;
    			} else if (pin == 37) {
    				CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK;
    			} else if (pin == 38) {
    				CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK;
    			} else if (pin == 39) {
    				CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK;
    			} else if (pin == 40) {
    				CORE_PIN40_PORTCLEAR = CORE_PIN40_BITMASK;
    			} else if (pin == 41) {
    				CORE_PIN41_PORTCLEAR = CORE_PIN41_BITMASK;
    			} else if (pin == 42) {
    				CORE_PIN42_PORTCLEAR = CORE_PIN42_BITMASK;
    			} else if (pin == 43) {
    				CORE_PIN43_PORTCLEAR = CORE_PIN43_BITMASK;
    			} else if (pin == 44) {
    				CORE_PIN44_PORTCLEAR = CORE_PIN44_BITMASK;
    			} else if (pin == 45) {
    				CORE_PIN45_PORTCLEAR = CORE_PIN45_BITMASK;
    			} else if (pin == 46) {
    				CORE_PIN46_PORTCLEAR = CORE_PIN46_BITMASK;
    			} else if (pin == 47) {
    				CORE_PIN47_PORTCLEAR = CORE_PIN47_BITMASK;
    			} else if (pin == 48) {
    				CORE_PIN48_PORTCLEAR = CORE_PIN48_BITMASK;
    			} else if (pin == 49) {
    				CORE_PIN49_PORTCLEAR = CORE_PIN49_BITMASK;
    			} else if (pin == 50) {
    				CORE_PIN50_PORTCLEAR = CORE_PIN50_BITMASK;
    			} else if (pin == 51) {
    				CORE_PIN51_PORTCLEAR = CORE_PIN51_BITMASK;
    			} else if (pin == 52) {
    				CORE_PIN52_PORTCLEAR = CORE_PIN52_BITMASK;
    			} else if (pin == 53) {
    				CORE_PIN53_PORTCLEAR = CORE_PIN53_BITMASK;
    			} else if (pin == 54) {
    				CORE_PIN54_PORTCLEAR = CORE_PIN54_BITMASK;
    			} else if (pin == 55) {
    				CORE_PIN55_PORTCLEAR = CORE_PIN55_BITMASK;
    			} else if (pin == 56) {
    				CORE_PIN56_PORTCLEAR = CORE_PIN56_BITMASK;
    			} else if (pin == 57) {
    				CORE_PIN57_PORTCLEAR = CORE_PIN57_BITMASK;
    			} else if (pin == 58) {
    				CORE_PIN58_PORTCLEAR = CORE_PIN58_BITMASK;
    			} else if (pin == 59) {
    				CORE_PIN59_PORTCLEAR = CORE_PIN59_BITMASK;
    			} else if (pin == 60) {
    				CORE_PIN60_PORTCLEAR = CORE_PIN60_BITMASK;
    			} else if (pin == 61) {
    				CORE_PIN61_PORTCLEAR = CORE_PIN61_BITMASK;
    			} else if (pin == 62) {
    				CORE_PIN62_PORTCLEAR = CORE_PIN62_BITMASK;
    			} else if (pin == 63) {
    				CORE_PIN63_PORTCLEAR = CORE_PIN63_BITMASK;
    			} else if (pin == 72) {
    				CORE_PIN72_PORTCLEAR = CORE_PIN72_BITMASK;
    			} else if (pin == 73) {
    				CORE_PIN73_PORTCLEAR = CORE_PIN73_BITMASK;
    			} else if (pin == 74) {
    				CORE_PIN74_PORTCLEAR = CORE_PIN74_BITMASK;
    			} else if (pin == 95) {
    				CORE_PIN95_PORTCLEAR = CORE_PIN95_BITMASK;
    			} else if (pin == 96) {
    				CORE_PIN96_PORTCLEAR = CORE_PIN96_BITMASK;
    			} else if (pin == 97) {
    				CORE_PIN97_PORTCLEAR = CORE_PIN97_BITMASK;
    			} else if (pin == 98) {
    				CORE_PIN98_PORTCLEAR = CORE_PIN98_BITMASK;
    			} else if (pin == 99) {
    				CORE_PIN99_PORTCLEAR = CORE_PIN99_BITMASK;
    			}
    			#endif
    		}
    	} else {
    		if (val) {
    			*portSetRegister(pin) = digitalPinToBitMask(pin);
    		} else {
    			*portClearRegister(pin) = digitalPinToBitMask(pin);
    		}
    	}
    }
    
    uint8_t digitalRead(uint8_t pin);
    static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused));
    static inline uint8_t digitalReadFast(uint8_t pin)
    {
    	if (__builtin_constant_p(pin)) {
    		if (pin == 0) {
    			return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0;
    		} else if (pin == 1) {
    			return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0;
    		} else if (pin == 2) {
    			return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0;
    		} else if (pin == 3) {
    			return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0;
    		} else if (pin == 4) {
    			return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0;
    		} else if (pin == 5) {
    			return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0;
    		} else if (pin == 6) {
    			return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0;
    		} else if (pin == 7) {
    			return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0;
    		} else if (pin == 8) {
    			return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0;
    		} else if (pin == 9) {
    			return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0;
    		} else if (pin == 10) {
    			return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0;
    		} else if (pin == 11) {
    			return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0;
    		} else if (pin == 12) {
    			return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0;
    		} else if (pin == 13) {
    			return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0;
    		} else if (pin == 14) {
    			return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0;
    		} else if (pin == 15) {
    			return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0;
    		} else if (pin == 16) {
    			return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0;
    		} else if (pin == 17) {
    			return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0;
    		} else if (pin == 18) {
    			return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0;
    		} else if (pin == 19) {
    			return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0;
    		} else if (pin == 20) {
    			return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0;
    		} else if (pin == 21) {
    			return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0;
    		} else if (pin == 22) {
    			return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0;
    		} else if (pin == 23) {
    			return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0;
    		} else if (pin == 24) {
    			return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0;
    		} else if (pin == 25) {
    			return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0;
    		} else if (pin == 26) {
    			return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0;
    		}
    		#if defined(CORE_PIN27_PINREG)
    		  else if (pin == 27) {
    			return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0;
    		} else if (pin == 28) {
    			return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0;
    		} else if (pin == 29) {
    			return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0;
    		} else if (pin == 30) {
    			return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0;
    		} else if (pin == 31) {
    			return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0;
    		} else if (pin == 32) {
    			return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;
    		} else if (pin == 33) {
    			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;
    		}
    		#endif
    		#if defined(CORE_PIN34_PINREG)
    		  else if (pin == 34) {
    			return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0;
    		} else if (pin == 35) {
    			return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0;
    		} else if (pin == 36) {
    			return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0;
    		} else if (pin == 37) {
    			return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0;
    		} else if (pin == 38) {
    			return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0;
    		} else if (pin == 39) {
    			return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0;
    		} else if (pin == 40) {
    			return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0;
    		} else if (pin == 41) {
    			return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0;
    		} else if (pin == 42) {
    			return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0;
    		} else if (pin == 43) {
    			return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0;
    		} else if (pin == 44) {
    			return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0;
    		} else if (pin == 45) {
    			return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0;
    		} else if (pin == 46) {
    			return (CORE_PIN46_PINREG & CORE_PIN46_BITMASK) ? 1 : 0;
    		} else if (pin == 47) {
    			return (CORE_PIN47_PINREG & CORE_PIN47_BITMASK) ? 1 : 0;
    		} else if (pin == 48) {
    			return (CORE_PIN48_PINREG & CORE_PIN48_BITMASK) ? 1 : 0;
    		} else if (pin == 49) {
    			return (CORE_PIN49_PINREG & CORE_PIN49_BITMASK) ? 1 : 0;
    		} else if (pin == 50) {
    			return (CORE_PIN50_PINREG & CORE_PIN50_BITMASK) ? 1 : 0;
    		} else if (pin == 51) {
    			return (CORE_PIN51_PINREG & CORE_PIN51_BITMASK) ? 1 : 0;
    		} else if (pin == 52) {
    			return (CORE_PIN52_PINREG & CORE_PIN52_BITMASK) ? 1 : 0;
    		} else if (pin == 53) {
    			return (CORE_PIN53_PINREG & CORE_PIN53_BITMASK) ? 1 : 0;
    		} else if (pin == 54) {
    			return (CORE_PIN54_PINREG & CORE_PIN54_BITMASK) ? 1 : 0;
    		} else if (pin == 55) {
    			return (CORE_PIN55_PINREG & CORE_PIN55_BITMASK) ? 1 : 0;
    		} else if (pin == 56) {
    			return (CORE_PIN56_PINREG & CORE_PIN56_BITMASK) ? 1 : 0;
    		} else if (pin == 57) {
    			return (CORE_PIN57_PINREG & CORE_PIN57_BITMASK) ? 1 : 0;
    		} else if (pin == 58) {
    			return (CORE_PIN58_PINREG & CORE_PIN58_BITMASK) ? 1 : 0;
    		} else if (pin == 59) {
    			return (CORE_PIN59_PINREG & CORE_PIN59_BITMASK) ? 1 : 0;
    		} else if (pin == 60) {
    			return (CORE_PIN60_PINREG & CORE_PIN60_BITMASK) ? 1 : 0;
    		} else if (pin == 61) {
    			return (CORE_PIN61_PINREG & CORE_PIN61_BITMASK) ? 1 : 0;
    		} else if (pin == 62) {
    			return (CORE_PIN62_PINREG & CORE_PIN62_BITMASK) ? 1 : 0;
    		} else if (pin == 63) {
    			return (CORE_PIN63_PINREG & CORE_PIN63_BITMASK) ? 1 : 0;
    		} else if (pin == 72) {
    			return (CORE_PIN72_PINREG & CORE_PIN72_BITMASK) ? 1 : 0;
    		} else if (pin == 73) {
    			return (CORE_PIN73_PINREG & CORE_PIN73_BITMASK) ? 1 : 0;
    		} else if (pin == 74) {
    			return (CORE_PIN74_PINREG & CORE_PIN74_BITMASK) ? 1 : 0;
    		} else if (pin == 95) {
    			return (CORE_PIN95_PINREG & CORE_PIN95_BITMASK) ? 1 : 0;
    		} else if (pin == 96) {
    			return (CORE_PIN96_PINREG & CORE_PIN96_BITMASK) ? 1 : 0;
    		} else if (pin == 97) {
    			return (CORE_PIN97_PINREG & CORE_PIN97_BITMASK) ? 1 : 0;
    		} else if (pin == 98) {
    			return (CORE_PIN98_PINREG & CORE_PIN98_BITMASK) ? 1 : 0;
    		} else if (pin == 99) {
    			return (CORE_PIN99_PINREG & CORE_PIN99_BITMASK) ? 1 : 0;
    		}
    		#endif
    		  else {
    			return 0;
    		}
    	} else {
    		#if defined(KINETISK)
    		return *portInputRegister(pin);
    		#else
    		return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0;
    		#endif
    	}
    }
    
    
    void pinMode(uint8_t pin, uint8_t mode);
    void init_pins(void);
    void analogWrite(uint8_t pin, int val);
    uint32_t analogWriteRes(uint32_t bits);
    static inline uint32_t analogWriteResolution(uint32_t bits) { return analogWriteRes(bits); }
    void analogWriteFrequency(uint8_t pin, float frequency);
    void analogWriteDAC0(int val);
    void analogWriteDAC1(int val);
    #ifdef __cplusplus
    void attachInterruptVector(IRQ_NUMBER_t irq, void (*function)(void));
    #else
    void attachInterruptVector(enum IRQ_NUMBER_t irq, void (*function)(void));
    #endif
    void attachInterrupt(uint8_t pin, void (*function)(void), int mode);
    void detachInterrupt(uint8_t pin);
    void _init_Teensyduino_internal_(void);
    
    int analogRead(uint8_t pin);
    void analogReference(uint8_t type);
    void analogReadRes(unsigned int bits);
    static inline void analogReadResolution(unsigned int bits) { analogReadRes(bits); }
    void analogReadAveraging(unsigned int num);
    void analog_init(void);
    
    
    
    #define DEFAULT         0
    #define INTERNAL        2
    #define INTERNAL1V2     2
    #define INTERNAL1V1     2
    #define EXTERNAL        0
    
    
    
    
    int touchRead(uint8_t pin);
    
    
    static inline void shiftOut(uint8_t, uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));
    extern void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) __attribute__((noinline));
    extern void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));
    extern void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));
    
    static inline void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)
    {
            if (__builtin_constant_p(bitOrder)) {
                    if (bitOrder == LSBFIRST) {
                            shiftOut_lsbFirst(dataPin, clockPin, value);
                    } else {
                            shiftOut_msbFirst(dataPin, clockPin, value);
                    }
            } else {
                    _shiftOut(dataPin, clockPin, bitOrder, value);
            }
    }
    
    static inline uint8_t shiftIn(uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));
    extern uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) __attribute__((noinline));
    extern uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));
    extern uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));
    
    static inline uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)
    {
            if (__builtin_constant_p(bitOrder)) {
                    if (bitOrder == LSBFIRST) {
                            return shiftIn_lsbFirst(dataPin, clockPin);
                    } else {
                            return shiftIn_msbFirst(dataPin, clockPin);
                    }
            } else {
                    return _shiftIn(dataPin, clockPin, bitOrder);
            }
    }
    
    void _reboot_Teensyduino_(void) __attribute__((noreturn));
    void _restart_Teensyduino_(void) __attribute__((noreturn));
    
    void yield(void);
    
    void delay(uint32_t msec);
    
    extern volatile uint32_t systick_millis_count;
    
    static inline uint32_t millis(void) __attribute__((always_inline, unused));
    static inline uint32_t millis(void)
    {
    	// Reading a volatile variable to another volatile
    	// seems redundant, but isn't for some cases.
    	// Eventually this should probably be replaced by a
    	// proper memory barrier or other technique.  Please
    	// do not remove this "redundant" code without
    	// carefully verifying the case mentioned here:
    	//
    	// https://forum.pjrc.com/threads/17469-millis%28%29-on-teensy-3?p=104924&viewfull=1#post104924
    	//
    	volatile uint32_t ret = systick_millis_count; // single aligned 32 bit is atomic
    	return ret;
    }
    
    uint32_t micros(void);
    
    static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));
    static inline void delayMicroseconds(uint32_t usec)
    {
    #if F_CPU == 240000000
    	uint32_t n = usec * 80;
    #elif F_CPU == 216000000
    	uint32_t n = usec * 72;
    #elif F_CPU == 192000000
    	uint32_t n = usec * 64;
    #elif F_CPU == 180000000
    	uint32_t n = usec * 60;
    #elif F_CPU == 168000000
    	uint32_t n = usec * 56;
    #elif F_CPU == 144000000
    	uint32_t n = usec * 48;
    #elif F_CPU == 120000000
    	uint32_t n = usec * 40;
    #elif F_CPU == 96000000
    	uint32_t n = usec << 5;
    #elif F_CPU == 72000000
    	uint32_t n = usec * 24;
    #elif F_CPU == 48000000
    	uint32_t n = usec << 4;
    #elif F_CPU == 24000000
    	uint32_t n = usec << 3;
    #elif F_CPU == 16000000
    	uint32_t n = usec << 2;
    #elif F_CPU == 8000000
    	uint32_t n = usec << 1;
    #elif F_CPU == 4000000
    	uint32_t n = usec;
    #elif F_CPU == 2000000
    	uint32_t n = usec >> 1;
    #endif
        // changed because a delay of 1 micro Sec @ 2MHz will be 0
    	if (n == 0) return;
    	__asm__ volatile(
    		"L_%=_delayMicroseconds:"		"\n\t"
    #if F_CPU < 24000000
    		"nop"					"\n\t"
    #endif
    #ifdef KINETISL
    		"sub    %0, #1"				"\n\t"
    #else
    		"subs   %0, #1"				"\n\t"
    #endif
    		"bne    L_%=_delayMicroseconds"		"\n"
    		: "+r" (n) :
    	);
    }
    
    #ifdef __cplusplus
    }
    #endif
    
    
    
    
    
    
    
    
    #ifdef __cplusplus
    extern "C" {
    #endif
    unsigned long rtc_get(void);
    void rtc_set(unsigned long t);
    void rtc_compensate(int adjust);
    #ifdef __cplusplus
    }
    class teensy3_clock_class
    {
    public:
    	static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); }
    	static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); }
    	static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); }
    };
    extern teensy3_clock_class Teensy3Clock;
    #endif
    
    
    
    
    #endif
    pins_teensy.c (add these lines after line 106)
    Code:
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN73_PORTREG, CORE_PIN73_BIT), &CORE_PIN73_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN74_PORTREG, CORE_PIN74_BIT), &CORE_PIN74_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN95_PORTREG, CORE_PIN95_BIT), &CORE_PIN95_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN96_PORTREG, CORE_PIN96_BIT), &CORE_PIN96_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN97_PORTREG, CORE_PIN97_BIT), &CORE_PIN97_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN98_PORTREG, CORE_PIN98_BIT), &CORE_PIN98_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN99_PORTREG, CORE_PIN99_BIT), &CORE_PIN99_CONFIG},  // new
    Pin tester code
    Code:
    /* 
     *  Simple Pin Test for Teensy Pro Extended GPIO
     *  Public Domain
    */
    
    
    void setup() {
      Serial.begin(115200);
      while (!Serial){}                  // Wait for USB
      Serial.println("*** Starting new pin test ***");
    
      for( uint8_t a = 97; a <= 99; a++){  // Initialize all new pins as outputs
        Serial.print(a);
        pinMode(a, OUTPUT);
        Serial.println(" - Intialized");
      }
    
    }
    
    
    
    void loop() {
      
      for( uint8_t a = 97; a <= 99; a++){ // Turn all new pins on
        digitalWrite(a, HIGH);   
      }
      Serial.println("ON");
      delay(750);
    
      
      for( uint8_t a = 97; a <= 99; a++){ // Turn all new pins off
        digitalWrite(a, LOW); 
      }
      Serial.println("     --OFF");
      delay(750);
      
    }

  23. #48
    Senior Member brtaylor's Avatar
    Join Date
    Mar 2016
    Location
    Portland, OR
    Posts
    584
    When you call pinMode, portConfigRegister is called, which is defined in pins_arduino.h. This is simply calling digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM from pins_teensy.c with the index of the pin number that you use. So with the way that you set up pins_teensy.c, PTA6 (Pin 72 in the new numbering scheme) is actually pin 64 when calling pinMode and digitalWrite. I just tested this and it works - I'm able to blink an LED on PTA6.

    So it seems like if we need to skip pin numbers, blank entries need to be added to the digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM table so the pin numbering matches up with the array index. I'm not sure if this is the best approach or if we should rethink the numbering scheme.

  24. #49
    Member
    Join Date
    Aug 2018
    Location
    Fort Worth, TX
    Posts
    38
    Of course it refers to the array index! I can't believe I missed that.

    For now, I'm inclined to pad the array and maintain the established numbering.

    I will finish populating the rest of the new pin numbers and test. Perhaps someone would like to help with the new ADC channels and UARTs? Home stretch here.

  25. #50
    Member
    Join Date
    Aug 2018
    Location
    Fort Worth, TX
    Posts
    38
    The following code seems to work roughly as expected (not exhaustively tested). Note the addition of the preprocessor directive "#define TEENSY_3_6_PRO" at the top of pins_teensy.c, enabling the extended IO definitions.

    core_pins.h
    Code:
    /* Extended pin definitions for standalone MK66 projects compatible with the Teensy 3.6 toolchain.
     * Based on Teensyduino Core Library - core_pins.h, V1.44
     * Copyright (c) 2017 PJRC.COM, LLC.
     
     * No affiliation with PJRC, no warranty or support expressed or implied.
     * https://forum.pjrc.com/threads/54114-Extended-Pin-Numbering
    */
    
    #ifndef _core_pins_h_
    #define _core_pins_h_
    
    #include "kinetis.h"
    #include "pins_arduino.h"
    
    #define HIGH		1
    #define LOW		0
    #define INPUT		0
    #define OUTPUT		1
    #define INPUT_PULLUP	2
    #define INPUT_PULLDOWN   3
    #define OUTPUT_OPENDRAIN 4
    #define INPUT_DISABLE   5
    #define LSBFIRST	0
    #define MSBFIRST	1
    #define _BV(n)		(1<<(n))
    #define CHANGE		4
    #define FALLING		2
    #define RISING		3
    
    
    #if defined(__MK66FX1M0__)
    #define CORE_NUM_TOTAL_PINS     100	// up from 64; double-check that these are all available
    #define CORE_NUM_DIGITAL        100	// up from 64; double-check that these are all available
    #define CORE_NUM_INTERRUPT      64	// need to research interrupt capabilities
    #define CORE_NUM_ANALOG         36  // double-check that these are all available
    #define CORE_NUM_PWM            22	// haven't looked at this
    #else 
    	#error "Incorrect processor selected! This library only compatible with NXP MK66/Teensy 3.6!"  // Guarantees that this library extension is not used with any non-target processors
    #endif
    
    // These MAX_PIN_PORTx values have the highest Kinetis pin index
    // that is used for a given port.
    #define CORE_MAX_PIN_PORTA        29
    #define CORE_MAX_PIN_PORTB        23
    #define CORE_MAX_PIN_PORTC        19	// Up from 11
    #define CORE_MAX_PIN_PORTD        15
    #define CORE_MAX_PIN_PORTE        28	// Up from 26
    
    //---- Begin new definitions
    // DO NOT DEFINE PTA0-4
    // 64-69 already defined in pins_arduino.h
    #define PTA5			25
    #define PTA6			72 // new
    #define PTA7			73 // new
    #define PTA8			74 // new
    #define PTA9			75 // new
    #define PTA10			76 // new
    #define PTA11			77 // new
    #define PTA12			3
    #define PTA13			4
    #define PTA14			26
    #define PTA15			27
    #define PTA16			28
    #define PTA17			39
    #define PTA24			78 // new
    #define PTA25			79 // new
    #define PTA26			42
    #define PTA27			80 // new
    #define PTA28			40
    #define PTA29			41
    #define PTB0			16
    #define PTB1			17
    #define PTB2			19
    #define PTB3			18
    #define PTB4			49
    #define PTB5			50
    #define PTB6			81 // new
    #define PTB7			82 // new
    #define PTB8			83 // new
    #define PTB9			84 // new
    #define PTB10			31
    #define PTB11			32
    #define PTB16			0
    #define PTB17			1
    #define PTB18			29
    #define PTB19			30
    #define PTB20			43
    #define PTB21			46
    #define PTB22			44
    #define PTB23			45
    #define PTC0			15
    #define PTC1			22
    #define PTC2			23
    #define PTC3			9
    #define PTC4			10
    #define PTC5			13
    #define PTC6			11
    #define PTC7			12
    #define PTC8			35
    #define PTC9			36
    #define PTC10			37
    #define PTC11			38
    #define PTC12			85 // new
    #define PTC13			86 // new
    #define PTC14			87 // new
    #define PTC15			88 // new
    #define PTC16			89 // new
    #define PTC17			90 // new
    #define PTC18			91 // new
    #define PTC19			92 // new
    #define PTD0			2
    #define PTD1			14
    #define PTD2			7
    #define PTD3			8
    #define PTD4			6
    #define PTD5			20
    #define PTD6			21
    #define PTD7			5
    #define PTD8			47
    #define PTD9			48
    #define PTD10			93 // new
    #define PTD11			55
    #define PTD12			53
    #define PTD13			52
    #define PTD14			51
    #define PTD15			54
    //#define PTE0			N/A Built In SD
    //#define PTE1			N/A Built In SD
    //#define PTE2			N/A Built In SD
    //#define PTE3			N/A Built In SD
    //#define PTE4			N/A Built In SD
    //#define PTE5			N/A Built In SD
    //#define PTE6			000  DO NOT DEFINE
    #define PTE7			94 // new
    #define PTE8			95 // new
    #define PTE9			96 // new
    #define PTE10			56
    #define PTE11			57
    #define PTE12			97 // new
    #define PTE24			33
    #define PTE25			34
    #define PTE26			24
    #define PTE27			98 // new
    #define PTE28			99 // new
    
    
    // PTA6
    #define CORE_PIN72_BIT		6
    #define CORE_PIN72_BITMASK	(1<<(CORE_PIN72_BIT))
    #define CORE_PIN72_PORTREG	GPIOA_PDOR
    #define CORE_PIN72_PORTSET	GPIOA_PSOR
    #define CORE_PIN72_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN72_DDRREG	GPIOA_PDDR
    #define CORE_PIN72_PINREG	GPIOA_PDIR
    #define CORE_PIN72_CONFIG	PORTA_PCR6
    #define CORE_INT72_PIN		72
    
    // PTA7
    #define CORE_PIN73_BIT		7
    #define CORE_PIN73_BITMASK	(1<<(CORE_PIN73_BIT))
    #define CORE_PIN73_PORTREG	GPIOA_PDOR
    #define CORE_PIN73_PORTSET	GPIOA_PSOR
    #define CORE_PIN73_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN73_DDRREG	GPIOA_PDDR
    #define CORE_PIN73_PINREG	GPIOA_PDIR
    #define CORE_PIN73_CONFIG	PORTA_PCR7
    #define CORE_INT73_PIN		73
    
    // PTA8
    #define CORE_PIN74_BIT		8
    #define CORE_PIN74_BITMASK	(1<<(CORE_PIN74_BIT))
    #define CORE_PIN74_PORTREG	GPIOA_PDOR
    #define CORE_PIN74_PORTSET	GPIOA_PSOR
    #define CORE_PIN74_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN74_DDRREG	GPIOA_PDDR
    #define CORE_PIN74_PINREG	GPIOA_PDIR
    #define CORE_PIN74_CONFIG	PORTA_PCR8
    #define CORE_INT74_PIN		74
    
    // PTA9
    #define CORE_PIN75_BIT		9
    #define CORE_PIN75_BITMASK	(1<<(CORE_PIN75_BIT))
    #define CORE_PIN75_PORTREG	GPIOA_PDOR
    #define CORE_PIN75_PORTSET	GPIOA_PSOR
    #define CORE_PIN75_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN75_DDRREG	GPIOA_PDDR
    #define CORE_PIN75_PINREG	GPIOA_PDIR
    #define CORE_PIN75_CONFIG	PORTA_PCR9
    #define CORE_INT75_PIN		75
    
    // PTA10
    #define CORE_PIN76_BIT		10
    #define CORE_PIN76_BITMASK	(1<<(CORE_PIN76_BIT))
    #define CORE_PIN76_PORTREG	GPIOA_PDOR
    #define CORE_PIN76_PORTSET	GPIOA_PSOR
    #define CORE_PIN76_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN76_DDRREG	GPIOA_PDDR
    #define CORE_PIN76_PINREG	GPIOA_PDIR
    #define CORE_PIN76_CONFIG	PORTA_PCR10
    #define CORE_INT76_PIN		76
    
    // PTA11
    #define CORE_PIN77_BIT		11
    #define CORE_PIN77_BITMASK	(1<<(CORE_PIN77_BIT))
    #define CORE_PIN77_PORTREG	GPIOA_PDOR
    #define CORE_PIN77_PORTSET	GPIOA_PSOR
    #define CORE_PIN77_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN77_DDRREG	GPIOA_PDDR
    #define CORE_PIN77_PINREG	GPIOA_PDIR
    #define CORE_PIN77_CONFIG	PORTA_PCR11
    #define CORE_INT77_PIN		77
    
    // PTA24
    #define CORE_PIN78_BIT		24
    #define CORE_PIN78_BITMASK	(1<<(CORE_PIN78_BIT))
    #define CORE_PIN78_PORTREG	GPIOA_PDOR
    #define CORE_PIN78_PORTSET	GPIOA_PSOR
    #define CORE_PIN78_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN78_DDRREG	GPIOA_PDDR
    #define CORE_PIN78_PINREG	GPIOA_PDIR
    #define CORE_PIN78_CONFIG	PORTA_PCR24
    #define CORE_INT78_PIN		78
    
    // PTA25
    #define CORE_PIN79_BIT		25
    #define CORE_PIN79_BITMASK	(1<<(CORE_PIN79_BIT))
    #define CORE_PIN79_PORTREG	GPIOA_PDOR
    #define CORE_PIN79_PORTSET	GPIOA_PSOR
    #define CORE_PIN79_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN79_DDRREG	GPIOA_PDDR
    #define CORE_PIN79_PINREG	GPIOA_PDIR
    #define CORE_PIN79_CONFIG	PORTA_PCR25
    #define CORE_INT79_PIN		79
    
    // PTA27
    #define CORE_PIN80_BIT		27
    #define CORE_PIN80_BITMASK	(1<<(CORE_PIN80_BIT))
    #define CORE_PIN80_PORTREG	GPIOA_PDOR
    #define CORE_PIN80_PORTSET	GPIOA_PSOR
    #define CORE_PIN80_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN80_DDRREG	GPIOA_PDDR
    #define CORE_PIN80_PINREG	GPIOA_PDIR
    #define CORE_PIN80_CONFIG	PORTA_PCR27
    #define CORE_INT80_PIN		80
    
    // PTB6
    #define CORE_PIN81_BIT		6
    #define CORE_PIN81_BITMASK	(1<<(CORE_PIN81_BIT))
    #define CORE_PIN81_PORTREG	GPIOB_PDOR
    #define CORE_PIN81_PORTSET	GPIOB_PSOR
    #define CORE_PIN81_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN81_DDRREG	GPIOB_PDDR
    #define CORE_PIN81_PINREG	GPIOB_PDIR
    #define CORE_PIN81_CONFIG	PORTB_PCR6
    #define CORE_INT81_PIN		81
    
    // PTB7
    #define CORE_PIN82_BIT		7
    #define CORE_PIN82_BITMASK	(1<<(CORE_PIN82_BIT))
    #define CORE_PIN82_PORTREG	GPIOB_PDOR
    #define CORE_PIN82_PORTSET	GPIOB_PSOR
    #define CORE_PIN82_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN82_DDRREG	GPIOB_PDDR
    #define CORE_PIN82_PINREG	GPIOB_PDIR
    #define CORE_PIN82_CONFIG	PORTB_PCR7
    #define CORE_INT82_PIN		82
    
    // PTB8
    #define CORE_PIN83_BIT		8
    #define CORE_PIN83_BITMASK	(1<<(CORE_PIN83_BIT))
    #define CORE_PIN83_PORTREG	GPIOB_PDOR
    #define CORE_PIN83_PORTSET	GPIOB_PSOR
    #define CORE_PIN83_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN83_DDRREG	GPIOB_PDDR
    #define CORE_PIN83_PINREG	GPIOB_PDIR
    #define CORE_PIN83_CONFIG	PORTB_PCR8
    #define CORE_INT83_PIN		83
    
    // PTB9
    #define CORE_PIN84_BIT		9
    #define CORE_PIN84_BITMASK	(1<<(CORE_PIN84_BIT))
    #define CORE_PIN84_PORTREG	GPIOB_PDOR
    #define CORE_PIN84_PORTSET	GPIOB_PSOR
    #define CORE_PIN84_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN84_DDRREG	GPIOB_PDDR
    #define CORE_PIN84_PINREG	GPIOB_PDIR
    #define CORE_PIN84_CONFIG	PORTB_PCR9
    #define CORE_INT84_PIN		84
    
    // PTC12
    #define CORE_PIN85_BIT		12
    #define CORE_PIN85_BITMASK	(1<<(CORE_PIN85_BIT))
    #define CORE_PIN85_PORTREG	GPIOC_PDOR
    #define CORE_PIN85_PORTSET	GPIOC_PSOR
    #define CORE_PIN85_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN85_DDRREG	GPIOC_PDDR
    #define CORE_PIN85_PINREG	GPIOC_PDIR
    #define CORE_PIN85_CONFIG	PORTC_PCR12
    #define CORE_INT85_PIN		85
    
    // PTC13
    #define CORE_PIN86_BIT		13
    #define CORE_PIN86_BITMASK	(1<<(CORE_PIN86_BIT))
    #define CORE_PIN86_PORTREG	GPIOC_PDOR
    #define CORE_PIN86_PORTSET	GPIOC_PSOR
    #define CORE_PIN86_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN86_DDRREG	GPIOC_PDDR
    #define CORE_PIN86_PINREG	GPIOC_PDIR
    #define CORE_PIN86_CONFIG	PORTC_PCR13
    #define CORE_INT86_PIN		86
    
    // PTC14
    #define CORE_PIN87_BIT		14
    #define CORE_PIN87_BITMASK	(1<<(CORE_PIN87_BIT))
    #define CORE_PIN87_PORTREG	GPIOC_PDOR
    #define CORE_PIN87_PORTSET	GPIOC_PSOR
    #define CORE_PIN87_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN87_DDRREG	GPIOC_PDDR
    #define CORE_PIN87_PINREG	GPIOC_PDIR
    #define CORE_PIN87_CONFIG	PORTC_PCR14
    #define CORE_INT87_PIN		87
    
    // PTC15
    #define CORE_PIN88_BIT		15
    #define CORE_PIN88_BITMASK	(1<<(CORE_PIN88_BIT))
    #define CORE_PIN88_PORTREG	GPIOC_PDOR
    #define CORE_PIN88_PORTSET	GPIOC_PSOR
    #define CORE_PIN88_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN88_DDRREG	GPIOC_PDDR
    #define CORE_PIN88_PINREG	GPIOC_PDIR
    #define CORE_PIN88_CONFIG	PORTC_PCR15
    #define CORE_INT88_PIN		88
    
    // PTC16
    #define CORE_PIN89_BIT		16
    #define CORE_PIN89_BITMASK	(1<<(CORE_PIN89_BIT))
    #define CORE_PIN89_PORTREG	GPIOC_PDOR
    #define CORE_PIN89_PORTSET	GPIOC_PSOR
    #define CORE_PIN89_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN89_DDRREG	GPIOC_PDDR
    #define CORE_PIN89_PINREG	GPIOC_PDIR
    #define CORE_PIN89_CONFIG	PORTC_PCR16
    #define CORE_INT89_PIN		89
    
    // PTC17
    #define CORE_PIN90_BIT		17
    #define CORE_PIN90_BITMASK	(1<<(CORE_PIN90_BIT))
    #define CORE_PIN90_PORTREG	GPIOC_PDOR
    #define CORE_PIN90_PORTSET	GPIOC_PSOR
    #define CORE_PIN90_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN90_DDRREG	GPIOC_PDDR
    #define CORE_PIN90_PINREG	GPIOC_PDIR
    #define CORE_PIN90_CONFIG	PORTC_PCR17
    #define CORE_INT90_PIN		90
    
    // PTC18
    #define CORE_PIN91_BIT		18
    #define CORE_PIN91_BITMASK	(1<<(CORE_PIN91_BIT))
    #define CORE_PIN91_PORTREG	GPIOC_PDOR
    #define CORE_PIN91_PORTSET	GPIOC_PSOR
    #define CORE_PIN91_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN91_DDRREG	GPIOC_PDDR
    #define CORE_PIN91_PINREG	GPIOC_PDIR
    #define CORE_PIN91_CONFIG	PORTC_PCR18
    #define CORE_INT91_PIN		91
    
    // PTC19
    #define CORE_PIN92_BIT		19
    #define CORE_PIN92_BITMASK	(1<<(CORE_PIN92_BIT))
    #define CORE_PIN92_PORTREG	GPIOC_PDOR
    #define CORE_PIN92_PORTSET	GPIOC_PSOR
    #define CORE_PIN92_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN92_DDRREG	GPIOC_PDDR
    #define CORE_PIN92_PINREG	GPIOC_PDIR
    #define CORE_PIN92_CONFIG	PORTC_PCR19
    #define CORE_INT92_PIN		92
    
    // PTD10
    #define CORE_PIN93_BIT		10
    #define CORE_PIN93_BITMASK	(1<<(CORE_PIN93_BIT))
    #define CORE_PIN93_PORTREG	GPIOD_PDOR
    #define CORE_PIN93_PORTSET	GPIOD_PSOR
    #define CORE_PIN93_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN93_DDRREG	GPIOD_PDDR
    #define CORE_PIN93_PINREG	GPIOD_PDIR
    #define CORE_PIN93_CONFIG	PORTD_PCR10
    #define CORE_INT93_PIN		93
    
    // PTE7
    #define CORE_PIN94_BIT		7
    #define CORE_PIN94_BITMASK	(1<<(CORE_PIN94_BIT))
    #define CORE_PIN94_PORTREG	GPIOE_PDOR
    #define CORE_PIN94_PORTSET	GPIOE_PSOR
    #define CORE_PIN94_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN94_DDRREG	GPIOE_PDDR
    #define CORE_PIN94_PINREG	GPIOE_PDIR
    #define CORE_PIN94_CONFIG	PORTE_PCR7
    #define CORE_INT94_PIN		94
    
    // PTE8
    #define CORE_PIN95_BIT		8
    #define CORE_PIN95_BITMASK	(1<<(CORE_PIN95_BIT))
    #define CORE_PIN95_PORTREG	GPIOE_PDOR
    #define CORE_PIN95_PORTSET	GPIOE_PSOR
    #define CORE_PIN95_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN95_DDRREG	GPIOE_PDDR
    #define CORE_PIN95_PINREG	GPIOE_PDIR
    #define CORE_PIN95_CONFIG	PORTE_PCR8
    #define CORE_INT95_PIN		95
    
    // PTE9
    #define CORE_PIN96_BIT		9
    #define CORE_PIN96_BITMASK	(1<<(CORE_PIN96_BIT))
    #define CORE_PIN96_PORTREG	GPIOE_PDOR
    #define CORE_PIN96_PORTSET	GPIOE_PSOR
    #define CORE_PIN96_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN96_DDRREG	GPIOE_PDDR
    #define CORE_PIN96_PINREG	GPIOE_PDIR
    #define CORE_PIN96_CONFIG	PORTE_PCR9
    #define CORE_INT96_PIN		96
    
    // PTE12
    #define CORE_PIN97_BIT		12
    #define CORE_PIN97_BITMASK	(1<<(CORE_PIN97_BIT))
    #define CORE_PIN97_PORTREG	GPIOE_PDOR
    #define CORE_PIN97_PORTSET	GPIOE_PSOR
    #define CORE_PIN97_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN97_DDRREG	GPIOE_PDDR
    #define CORE_PIN97_PINREG	GPIOE_PDIR
    #define CORE_PIN97_CONFIG	PORTE_PCR12
    #define CORE_INT97_PIN		97
    
    // PTE27
    #define CORE_PIN98_BIT		27
    #define CORE_PIN98_BITMASK	(1<<(CORE_PIN98_BIT))
    #define CORE_PIN98_PORTREG	GPIOE_PDOR
    #define CORE_PIN98_PORTSET	GPIOE_PSOR
    #define CORE_PIN98_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN98_DDRREG	GPIOE_PDDR
    #define CORE_PIN98_PINREG	GPIOE_PDIR
    #define CORE_PIN98_CONFIG	PORTE_PCR27
    #define CORE_INT98_PIN		98
    
    // PTE28
    #define CORE_PIN99_BIT		28
    #define CORE_PIN99_BITMASK	(1<<(CORE_PIN99_BIT))
    #define CORE_PIN99_PORTREG	GPIOE_PDOR
    #define CORE_PIN99_PORTSET	GPIOE_PSOR
    #define CORE_PIN99_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN99_DDRREG	GPIOE_PDDR
    #define CORE_PIN99_PINREG	GPIOE_PDIR
    #define CORE_PIN99_CONFIG	PORTE_PCR28
    #define CORE_INT99_PIN		99
    
    
    
    
    //---- End new definitions
    
    
    #define CORE_PIN0_BIT		16
    #define CORE_PIN1_BIT		17
    #define CORE_PIN2_BIT		0
    #define CORE_PIN3_BIT		12
    #define CORE_PIN4_BIT		13
    #define CORE_PIN5_BIT		7
    #define CORE_PIN6_BIT		4
    #define CORE_PIN7_BIT		2
    #define CORE_PIN8_BIT		3
    #define CORE_PIN9_BIT		3
    #define CORE_PIN10_BIT		4
    #define CORE_PIN11_BIT		6
    #define CORE_PIN12_BIT		7
    #define CORE_PIN13_BIT		5
    #define CORE_PIN14_BIT		1
    #define CORE_PIN15_BIT		0
    #define CORE_PIN16_BIT		0
    #define CORE_PIN17_BIT		1
    #define CORE_PIN18_BIT		3
    #define CORE_PIN19_BIT		2
    #define CORE_PIN20_BIT		5
    #define CORE_PIN21_BIT		6
    #define CORE_PIN22_BIT		1
    #define CORE_PIN23_BIT		2
    #define CORE_PIN24_BIT		26
    #define CORE_PIN25_BIT		5
    #define CORE_PIN26_BIT		14
    #define CORE_PIN27_BIT		15
    #define CORE_PIN28_BIT		16
    #define CORE_PIN29_BIT		18
    #define CORE_PIN30_BIT		19
    #define CORE_PIN31_BIT		10
    #define CORE_PIN32_BIT		11
    #define CORE_PIN33_BIT		24
    #define CORE_PIN34_BIT		25
    #define CORE_PIN35_BIT		8
    #define CORE_PIN36_BIT		9
    #define CORE_PIN37_BIT		10
    #define CORE_PIN38_BIT		11
    #define CORE_PIN39_BIT		17
    #define CORE_PIN40_BIT		28
    #define CORE_PIN41_BIT		29
    #define CORE_PIN42_BIT		26
    #define CORE_PIN43_BIT		20
    #define CORE_PIN44_BIT		22
    #define CORE_PIN45_BIT		23
    #define CORE_PIN46_BIT		21
    #define CORE_PIN47_BIT		8
    #define CORE_PIN48_BIT		9
    #define CORE_PIN49_BIT		4
    #define CORE_PIN50_BIT		5
    #define CORE_PIN51_BIT		14
    #define CORE_PIN52_BIT		13
    #define CORE_PIN53_BIT		12
    #define CORE_PIN54_BIT		15
    #define CORE_PIN55_BIT		11
    #define CORE_PIN56_BIT		10
    #define CORE_PIN57_BIT		11
    #define CORE_PIN58_BIT		0
    #define CORE_PIN59_BIT		1
    #define CORE_PIN60_BIT		2
    #define CORE_PIN61_BIT		3
    #define CORE_PIN62_BIT		4
    #define CORE_PIN63_BIT		5
    
    #define CORE_PIN0_BITMASK	(1<<(CORE_PIN0_BIT))
    #define CORE_PIN1_BITMASK	(1<<(CORE_PIN1_BIT))
    #define CORE_PIN2_BITMASK	(1<<(CORE_PIN2_BIT))
    #define CORE_PIN3_BITMASK	(1<<(CORE_PIN3_BIT))
    #define CORE_PIN4_BITMASK	(1<<(CORE_PIN4_BIT))
    #define CORE_PIN5_BITMASK	(1<<(CORE_PIN5_BIT))
    #define CORE_PIN6_BITMASK	(1<<(CORE_PIN6_BIT))
    #define CORE_PIN7_BITMASK	(1<<(CORE_PIN7_BIT))
    #define CORE_PIN8_BITMASK	(1<<(CORE_PIN8_BIT))
    #define CORE_PIN9_BITMASK	(1<<(CORE_PIN9_BIT))
    #define CORE_PIN10_BITMASK	(1<<(CORE_PIN10_BIT))
    #define CORE_PIN11_BITMASK	(1<<(CORE_PIN11_BIT))
    #define CORE_PIN12_BITMASK	(1<<(CORE_PIN12_BIT))
    #define CORE_PIN13_BITMASK	(1<<(CORE_PIN13_BIT))
    #define CORE_PIN14_BITMASK	(1<<(CORE_PIN14_BIT))
    #define CORE_PIN15_BITMASK	(1<<(CORE_PIN15_BIT))
    #define CORE_PIN16_BITMASK	(1<<(CORE_PIN16_BIT))
    #define CORE_PIN17_BITMASK	(1<<(CORE_PIN17_BIT))
    #define CORE_PIN18_BITMASK	(1<<(CORE_PIN18_BIT))
    #define CORE_PIN19_BITMASK	(1<<(CORE_PIN19_BIT))
    #define CORE_PIN20_BITMASK	(1<<(CORE_PIN20_BIT))
    #define CORE_PIN21_BITMASK	(1<<(CORE_PIN21_BIT))
    #define CORE_PIN22_BITMASK	(1<<(CORE_PIN22_BIT))
    #define CORE_PIN23_BITMASK	(1<<(CORE_PIN23_BIT))
    #define CORE_PIN24_BITMASK	(1<<(CORE_PIN24_BIT))
    #define CORE_PIN25_BITMASK	(1<<(CORE_PIN25_BIT))
    #define CORE_PIN26_BITMASK	(1<<(CORE_PIN26_BIT))
    #define CORE_PIN27_BITMASK	(1<<(CORE_PIN27_BIT))
    #define CORE_PIN28_BITMASK	(1<<(CORE_PIN28_BIT))
    #define CORE_PIN29_BITMASK	(1<<(CORE_PIN29_BIT))
    #define CORE_PIN30_BITMASK	(1<<(CORE_PIN30_BIT))
    #define CORE_PIN31_BITMASK	(1<<(CORE_PIN31_BIT))
    #define CORE_PIN32_BITMASK	(1<<(CORE_PIN32_BIT))
    #define CORE_PIN33_BITMASK	(1<<(CORE_PIN33_BIT))
    #define CORE_PIN34_BITMASK	(1<<(CORE_PIN34_BIT))
    #define CORE_PIN35_BITMASK	(1<<(CORE_PIN35_BIT))
    #define CORE_PIN36_BITMASK	(1<<(CORE_PIN36_BIT))
    #define CORE_PIN37_BITMASK	(1<<(CORE_PIN37_BIT))
    #define CORE_PIN38_BITMASK	(1<<(CORE_PIN38_BIT))
    #define CORE_PIN39_BITMASK	(1<<(CORE_PIN39_BIT))
    #define CORE_PIN40_BITMASK	(1<<(CORE_PIN40_BIT))
    #define CORE_PIN41_BITMASK	(1<<(CORE_PIN41_BIT))
    #define CORE_PIN42_BITMASK	(1<<(CORE_PIN42_BIT))
    #define CORE_PIN43_BITMASK	(1<<(CORE_PIN43_BIT))
    #define CORE_PIN44_BITMASK	(1<<(CORE_PIN44_BIT))
    #define CORE_PIN45_BITMASK	(1<<(CORE_PIN45_BIT))
    #define CORE_PIN46_BITMASK	(1<<(CORE_PIN46_BIT))
    #define CORE_PIN47_BITMASK	(1<<(CORE_PIN47_BIT))
    #define CORE_PIN48_BITMASK	(1<<(CORE_PIN48_BIT))
    #define CORE_PIN49_BITMASK	(1<<(CORE_PIN49_BIT))
    #define CORE_PIN50_BITMASK	(1<<(CORE_PIN50_BIT))
    #define CORE_PIN51_BITMASK	(1<<(CORE_PIN51_BIT))
    #define CORE_PIN52_BITMASK	(1<<(CORE_PIN52_BIT))
    #define CORE_PIN53_BITMASK	(1<<(CORE_PIN53_BIT))
    #define CORE_PIN54_BITMASK	(1<<(CORE_PIN54_BIT))
    #define CORE_PIN55_BITMASK	(1<<(CORE_PIN55_BIT))
    #define CORE_PIN56_BITMASK	(1<<(CORE_PIN56_BIT))
    #define CORE_PIN57_BITMASK	(1<<(CORE_PIN57_BIT))
    #define CORE_PIN58_BITMASK	(1<<(CORE_PIN58_BIT))
    #define CORE_PIN59_BITMASK	(1<<(CORE_PIN59_BIT))
    #define CORE_PIN60_BITMASK	(1<<(CORE_PIN60_BIT))
    #define CORE_PIN61_BITMASK	(1<<(CORE_PIN61_BIT))
    #define CORE_PIN62_BITMASK	(1<<(CORE_PIN62_BIT))
    #define CORE_PIN63_BITMASK	(1<<(CORE_PIN63_BIT))
    
    
    #define CORE_PIN0_PORTREG	GPIOB_PDOR
    #define CORE_PIN1_PORTREG	GPIOB_PDOR
    #define CORE_PIN2_PORTREG	GPIOD_PDOR
    #define CORE_PIN3_PORTREG	GPIOA_PDOR
    #define CORE_PIN4_PORTREG	GPIOA_PDOR
    #define CORE_PIN5_PORTREG	GPIOD_PDOR
    #define CORE_PIN6_PORTREG	GPIOD_PDOR
    #define CORE_PIN7_PORTREG	GPIOD_PDOR
    #define CORE_PIN8_PORTREG	GPIOD_PDOR
    #define CORE_PIN9_PORTREG	GPIOC_PDOR
    #define CORE_PIN10_PORTREG	GPIOC_PDOR
    #define CORE_PIN11_PORTREG	GPIOC_PDOR
    #define CORE_PIN12_PORTREG	GPIOC_PDOR
    #define CORE_PIN13_PORTREG	GPIOC_PDOR
    #define CORE_PIN14_PORTREG	GPIOD_PDOR
    #define CORE_PIN15_PORTREG	GPIOC_PDOR
    #define CORE_PIN16_PORTREG	GPIOB_PDOR
    #define CORE_PIN17_PORTREG	GPIOB_PDOR
    #define CORE_PIN18_PORTREG	GPIOB_PDOR
    #define CORE_PIN19_PORTREG	GPIOB_PDOR
    #define CORE_PIN20_PORTREG	GPIOD_PDOR
    #define CORE_PIN21_PORTREG	GPIOD_PDOR
    #define CORE_PIN22_PORTREG	GPIOC_PDOR
    #define CORE_PIN23_PORTREG	GPIOC_PDOR
    #define CORE_PIN24_PORTREG	GPIOE_PDOR
    #define CORE_PIN25_PORTREG	GPIOA_PDOR
    #define CORE_PIN26_PORTREG	GPIOA_PDOR
    #define CORE_PIN27_PORTREG	GPIOA_PDOR
    #define CORE_PIN28_PORTREG	GPIOA_PDOR
    #define CORE_PIN29_PORTREG	GPIOB_PDOR
    #define CORE_PIN30_PORTREG	GPIOB_PDOR
    #define CORE_PIN31_PORTREG	GPIOB_PDOR
    #define CORE_PIN32_PORTREG	GPIOB_PDOR
    #define CORE_PIN33_PORTREG	GPIOE_PDOR
    #define CORE_PIN34_PORTREG	GPIOE_PDOR
    #define CORE_PIN35_PORTREG	GPIOC_PDOR
    #define CORE_PIN36_PORTREG	GPIOC_PDOR
    #define CORE_PIN37_PORTREG	GPIOC_PDOR
    #define CORE_PIN38_PORTREG	GPIOC_PDOR
    #define CORE_PIN39_PORTREG	GPIOA_PDOR
    #define CORE_PIN40_PORTREG	GPIOA_PDOR
    #define CORE_PIN41_PORTREG	GPIOA_PDOR
    #define CORE_PIN42_PORTREG	GPIOA_PDOR
    #define CORE_PIN43_PORTREG	GPIOB_PDOR
    #define CORE_PIN44_PORTREG	GPIOB_PDOR
    #define CORE_PIN45_PORTREG	GPIOB_PDOR
    #define CORE_PIN46_PORTREG	GPIOB_PDOR
    #define CORE_PIN47_PORTREG	GPIOD_PDOR
    #define CORE_PIN48_PORTREG	GPIOD_PDOR
    #define CORE_PIN49_PORTREG	GPIOB_PDOR
    #define CORE_PIN50_PORTREG	GPIOB_PDOR
    #define CORE_PIN51_PORTREG	GPIOD_PDOR
    #define CORE_PIN52_PORTREG	GPIOD_PDOR
    #define CORE_PIN53_PORTREG	GPIOD_PDOR
    #define CORE_PIN54_PORTREG	GPIOD_PDOR
    #define CORE_PIN55_PORTREG	GPIOD_PDOR
    #define CORE_PIN56_PORTREG	GPIOE_PDOR
    #define CORE_PIN57_PORTREG	GPIOE_PDOR
    #define CORE_PIN58_PORTREG	GPIOE_PDOR
    #define CORE_PIN59_PORTREG	GPIOE_PDOR
    #define CORE_PIN60_PORTREG	GPIOE_PDOR
    #define CORE_PIN61_PORTREG	GPIOE_PDOR
    #define CORE_PIN62_PORTREG	GPIOE_PDOR
    #define CORE_PIN63_PORTREG	GPIOE_PDOR
    
    #define CORE_PIN0_PORTSET	GPIOB_PSOR
    #define CORE_PIN1_PORTSET	GPIOB_PSOR
    #define CORE_PIN2_PORTSET	GPIOD_PSOR
    #define CORE_PIN3_PORTSET	GPIOA_PSOR
    #define CORE_PIN4_PORTSET	GPIOA_PSOR
    #define CORE_PIN5_PORTSET	GPIOD_PSOR
    #define CORE_PIN6_PORTSET	GPIOD_PSOR
    #define CORE_PIN7_PORTSET	GPIOD_PSOR
    #define CORE_PIN8_PORTSET	GPIOD_PSOR
    #define CORE_PIN9_PORTSET	GPIOC_PSOR
    #define CORE_PIN10_PORTSET	GPIOC_PSOR
    #define CORE_PIN11_PORTSET	GPIOC_PSOR
    #define CORE_PIN12_PORTSET	GPIOC_PSOR
    #define CORE_PIN13_PORTSET	GPIOC_PSOR
    #define CORE_PIN14_PORTSET	GPIOD_PSOR
    #define CORE_PIN15_PORTSET	GPIOC_PSOR
    #define CORE_PIN16_PORTSET	GPIOB_PSOR
    #define CORE_PIN17_PORTSET	GPIOB_PSOR
    #define CORE_PIN18_PORTSET	GPIOB_PSOR
    #define CORE_PIN19_PORTSET	GPIOB_PSOR
    #define CORE_PIN20_PORTSET	GPIOD_PSOR
    #define CORE_PIN21_PORTSET	GPIOD_PSOR
    #define CORE_PIN22_PORTSET	GPIOC_PSOR
    #define CORE_PIN23_PORTSET	GPIOC_PSOR
    #define CORE_PIN24_PORTSET	GPIOE_PSOR
    #define CORE_PIN25_PORTSET	GPIOA_PSOR
    #define CORE_PIN26_PORTSET	GPIOA_PSOR
    #define CORE_PIN27_PORTSET	GPIOA_PSOR
    #define CORE_PIN28_PORTSET	GPIOA_PSOR
    #define CORE_PIN29_PORTSET	GPIOB_PSOR
    #define CORE_PIN30_PORTSET	GPIOB_PSOR
    #define CORE_PIN31_PORTSET	GPIOB_PSOR
    #define CORE_PIN32_PORTSET	GPIOB_PSOR
    #define CORE_PIN33_PORTSET	GPIOE_PSOR
    #define CORE_PIN34_PORTSET	GPIOE_PSOR
    #define CORE_PIN35_PORTSET	GPIOC_PSOR
    #define CORE_PIN36_PORTSET	GPIOC_PSOR
    #define CORE_PIN37_PORTSET	GPIOC_PSOR
    #define CORE_PIN38_PORTSET	GPIOC_PSOR
    #define CORE_PIN39_PORTSET	GPIOA_PSOR
    #define CORE_PIN40_PORTSET	GPIOA_PSOR
    #define CORE_PIN41_PORTSET	GPIOA_PSOR
    #define CORE_PIN42_PORTSET	GPIOA_PSOR
    #define CORE_PIN43_PORTSET	GPIOB_PSOR
    #define CORE_PIN44_PORTSET	GPIOB_PSOR
    #define CORE_PIN45_PORTSET	GPIOB_PSOR
    #define CORE_PIN46_PORTSET	GPIOB_PSOR
    #define CORE_PIN47_PORTSET	GPIOD_PSOR
    #define CORE_PIN48_PORTSET	GPIOD_PSOR
    #define CORE_PIN49_PORTSET	GPIOB_PSOR
    #define CORE_PIN50_PORTSET	GPIOB_PSOR
    #define CORE_PIN51_PORTSET	GPIOD_PSOR
    #define CORE_PIN52_PORTSET	GPIOD_PSOR
    #define CORE_PIN53_PORTSET	GPIOD_PSOR
    #define CORE_PIN54_PORTSET	GPIOD_PSOR
    #define CORE_PIN55_PORTSET	GPIOD_PSOR
    #define CORE_PIN56_PORTSET	GPIOE_PSOR
    #define CORE_PIN57_PORTSET	GPIOE_PSOR
    #define CORE_PIN58_PORTSET	GPIOE_PSOR
    #define CORE_PIN59_PORTSET	GPIOE_PSOR
    #define CORE_PIN60_PORTSET	GPIOE_PSOR
    #define CORE_PIN61_PORTSET	GPIOE_PSOR
    #define CORE_PIN62_PORTSET	GPIOE_PSOR
    #define CORE_PIN63_PORTSET	GPIOE_PSOR
    
    #define CORE_PIN0_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN1_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN2_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN3_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN4_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN5_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN6_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN7_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN8_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN9_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN10_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN11_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN12_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN13_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN14_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN15_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN16_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN17_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN18_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN19_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN20_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN21_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN22_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN23_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN24_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN25_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN26_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN27_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN28_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN29_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN30_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN31_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN32_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN33_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN34_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN35_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN36_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN37_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN38_PORTCLEAR	GPIOC_PCOR
    #define CORE_PIN39_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN40_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN41_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN42_PORTCLEAR	GPIOA_PCOR
    #define CORE_PIN43_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN44_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN45_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN46_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN47_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN48_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN49_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN50_PORTCLEAR	GPIOB_PCOR
    #define CORE_PIN51_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN52_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN53_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN54_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN55_PORTCLEAR	GPIOD_PCOR
    #define CORE_PIN56_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN57_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN58_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN59_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN60_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN61_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN62_PORTCLEAR	GPIOE_PCOR
    #define CORE_PIN63_PORTCLEAR	GPIOE_PCOR
    
    #define CORE_PIN0_DDRREG	GPIOB_PDDR
    #define CORE_PIN1_DDRREG	GPIOB_PDDR
    #define CORE_PIN2_DDRREG	GPIOD_PDDR
    #define CORE_PIN3_DDRREG	GPIOA_PDDR
    #define CORE_PIN4_DDRREG	GPIOA_PDDR
    #define CORE_PIN5_DDRREG	GPIOD_PDDR
    #define CORE_PIN6_DDRREG	GPIOD_PDDR
    #define CORE_PIN7_DDRREG	GPIOD_PDDR
    #define CORE_PIN8_DDRREG	GPIOD_PDDR
    #define CORE_PIN9_DDRREG	GPIOC_PDDR
    #define CORE_PIN10_DDRREG	GPIOC_PDDR
    #define CORE_PIN11_DDRREG	GPIOC_PDDR
    #define CORE_PIN12_DDRREG	GPIOC_PDDR
    #define CORE_PIN13_DDRREG	GPIOC_PDDR
    #define CORE_PIN14_DDRREG	GPIOD_PDDR
    #define CORE_PIN15_DDRREG	GPIOC_PDDR
    #define CORE_PIN16_DDRREG	GPIOB_PDDR
    #define CORE_PIN17_DDRREG	GPIOB_PDDR
    #define CORE_PIN18_DDRREG	GPIOB_PDDR
    #define CORE_PIN19_DDRREG	GPIOB_PDDR
    #define CORE_PIN20_DDRREG	GPIOD_PDDR
    #define CORE_PIN21_DDRREG	GPIOD_PDDR
    #define CORE_PIN22_DDRREG	GPIOC_PDDR
    #define CORE_PIN23_DDRREG	GPIOC_PDDR
    #define CORE_PIN24_DDRREG	GPIOE_PDDR
    #define CORE_PIN25_DDRREG	GPIOA_PDDR
    #define CORE_PIN26_DDRREG	GPIOA_PDDR
    #define CORE_PIN27_DDRREG	GPIOA_PDDR
    #define CORE_PIN28_DDRREG	GPIOA_PDDR
    #define CORE_PIN29_DDRREG	GPIOB_PDDR
    #define CORE_PIN30_DDRREG	GPIOB_PDDR
    #define CORE_PIN31_DDRREG	GPIOB_PDDR
    #define CORE_PIN32_DDRREG	GPIOB_PDDR
    #define CORE_PIN33_DDRREG	GPIOE_PDDR
    #define CORE_PIN34_DDRREG	GPIOE_PDDR
    #define CORE_PIN35_DDRREG	GPIOC_PDDR
    #define CORE_PIN36_DDRREG	GPIOC_PDDR
    #define CORE_PIN37_DDRREG	GPIOC_PDDR
    #define CORE_PIN38_DDRREG	GPIOC_PDDR
    #define CORE_PIN39_DDRREG	GPIOA_PDDR
    #define CORE_PIN40_DDRREG	GPIOA_PDDR
    #define CORE_PIN41_DDRREG	GPIOA_PDDR
    #define CORE_PIN42_DDRREG	GPIOA_PDDR
    #define CORE_PIN43_DDRREG	GPIOB_PDDR
    #define CORE_PIN44_DDRREG	GPIOB_PDDR
    #define CORE_PIN45_DDRREG	GPIOB_PDDR
    #define CORE_PIN46_DDRREG	GPIOB_PDDR
    #define CORE_PIN47_DDRREG	GPIOD_PDDR
    #define CORE_PIN48_DDRREG	GPIOD_PDDR
    #define CORE_PIN49_DDRREG	GPIOB_PDDR
    #define CORE_PIN50_DDRREG	GPIOB_PDDR
    #define CORE_PIN51_DDRREG	GPIOD_PDDR
    #define CORE_PIN52_DDRREG	GPIOD_PDDR
    #define CORE_PIN53_DDRREG	GPIOD_PDDR
    #define CORE_PIN54_DDRREG	GPIOD_PDDR
    #define CORE_PIN55_DDRREG	GPIOD_PDDR
    #define CORE_PIN56_DDRREG	GPIOE_PDDR
    #define CORE_PIN57_DDRREG	GPIOE_PDDR
    #define CORE_PIN58_DDRREG	GPIOE_PDDR
    #define CORE_PIN59_DDRREG	GPIOE_PDDR
    #define CORE_PIN60_DDRREG	GPIOE_PDDR
    #define CORE_PIN61_DDRREG	GPIOE_PDDR
    #define CORE_PIN62_DDRREG	GPIOE_PDDR
    #define CORE_PIN63_DDRREG	GPIOE_PDDR
    
    #define CORE_PIN0_PINREG	GPIOB_PDIR
    #define CORE_PIN1_PINREG	GPIOB_PDIR
    #define CORE_PIN2_PINREG	GPIOD_PDIR
    #define CORE_PIN3_PINREG	GPIOA_PDIR
    #define CORE_PIN4_PINREG	GPIOA_PDIR
    #define CORE_PIN5_PINREG	GPIOD_PDIR
    #define CORE_PIN6_PINREG	GPIOD_PDIR
    #define CORE_PIN7_PINREG	GPIOD_PDIR
    #define CORE_PIN8_PINREG	GPIOD_PDIR
    #define CORE_PIN9_PINREG	GPIOC_PDIR
    #define CORE_PIN10_PINREG	GPIOC_PDIR
    #define CORE_PIN11_PINREG	GPIOC_PDIR
    #define CORE_PIN12_PINREG	GPIOC_PDIR
    #define CORE_PIN13_PINREG	GPIOC_PDIR
    #define CORE_PIN14_PINREG	GPIOD_PDIR
    #define CORE_PIN15_PINREG	GPIOC_PDIR
    #define CORE_PIN16_PINREG	GPIOB_PDIR
    #define CORE_PIN17_PINREG	GPIOB_PDIR
    #define CORE_PIN18_PINREG	GPIOB_PDIR
    #define CORE_PIN19_PINREG	GPIOB_PDIR
    #define CORE_PIN20_PINREG	GPIOD_PDIR
    #define CORE_PIN21_PINREG	GPIOD_PDIR
    #define CORE_PIN22_PINREG	GPIOC_PDIR
    #define CORE_PIN23_PINREG	GPIOC_PDIR
    #define CORE_PIN24_PINREG	GPIOE_PDIR
    #define CORE_PIN25_PINREG	GPIOA_PDIR
    #define CORE_PIN26_PINREG	GPIOA_PDIR
    #define CORE_PIN27_PINREG	GPIOA_PDIR
    #define CORE_PIN28_PINREG	GPIOA_PDIR
    #define CORE_PIN29_PINREG	GPIOB_PDIR
    #define CORE_PIN30_PINREG	GPIOB_PDIR
    #define CORE_PIN31_PINREG	GPIOB_PDIR
    #define CORE_PIN32_PINREG	GPIOB_PDIR
    #define CORE_PIN33_PINREG	GPIOE_PDIR
    #define CORE_PIN34_PINREG	GPIOE_PDIR
    #define CORE_PIN35_PINREG	GPIOC_PDIR
    #define CORE_PIN36_PINREG	GPIOC_PDIR
    #define CORE_PIN37_PINREG	GPIOC_PDIR
    #define CORE_PIN38_PINREG	GPIOC_PDIR
    #define CORE_PIN39_PINREG	GPIOA_PDIR
    #define CORE_PIN40_PINREG	GPIOA_PDIR
    #define CORE_PIN41_PINREG	GPIOA_PDIR
    #define CORE_PIN42_PINREG	GPIOA_PDIR
    #define CORE_PIN43_PINREG	GPIOB_PDIR
    #define CORE_PIN44_PINREG	GPIOB_PDIR
    #define CORE_PIN45_PINREG	GPIOB_PDIR
    #define CORE_PIN46_PINREG	GPIOB_PDIR
    #define CORE_PIN47_PINREG	GPIOD_PDIR
    #define CORE_PIN48_PINREG	GPIOD_PDIR
    #define CORE_PIN49_PINREG	GPIOB_PDIR
    #define CORE_PIN50_PINREG	GPIOB_PDIR
    #define CORE_PIN51_PINREG	GPIOD_PDIR
    #define CORE_PIN52_PINREG	GPIOD_PDIR
    #define CORE_PIN53_PINREG	GPIOD_PDIR
    #define CORE_PIN54_PINREG	GPIOD_PDIR
    #define CORE_PIN55_PINREG	GPIOD_PDIR
    #define CORE_PIN56_PINREG	GPIOE_PDIR
    #define CORE_PIN57_PINREG	GPIOE_PDIR
    #define CORE_PIN58_PINREG	GPIOE_PDIR
    #define CORE_PIN59_PINREG	GPIOE_PDIR
    #define CORE_PIN60_PINREG	GPIOE_PDIR
    #define CORE_PIN61_PINREG	GPIOE_PDIR
    #define CORE_PIN62_PINREG	GPIOE_PDIR
    #define CORE_PIN63_PINREG	GPIOE_PDIR
    
    #define CORE_PIN0_CONFIG	PORTB_PCR16
    #define CORE_PIN1_CONFIG	PORTB_PCR17
    #define CORE_PIN2_CONFIG	PORTD_PCR0
    #define CORE_PIN3_CONFIG	PORTA_PCR12
    #define CORE_PIN4_CONFIG	PORTA_PCR13
    #define CORE_PIN5_CONFIG	PORTD_PCR7
    #define CORE_PIN6_CONFIG	PORTD_PCR4
    #define CORE_PIN7_CONFIG	PORTD_PCR2
    #define CORE_PIN8_CONFIG	PORTD_PCR3
    #define CORE_PIN9_CONFIG	PORTC_PCR3
    #define CORE_PIN10_CONFIG	PORTC_PCR4
    #define CORE_PIN11_CONFIG	PORTC_PCR6
    #define CORE_PIN12_CONFIG	PORTC_PCR7
    #define CORE_PIN13_CONFIG	PORTC_PCR5
    #define CORE_PIN14_CONFIG	PORTD_PCR1
    #define CORE_PIN15_CONFIG	PORTC_PCR0
    #define CORE_PIN16_CONFIG	PORTB_PCR0
    #define CORE_PIN17_CONFIG	PORTB_PCR1
    #define CORE_PIN18_CONFIG	PORTB_PCR3
    #define CORE_PIN19_CONFIG	PORTB_PCR2
    #define CORE_PIN20_CONFIG	PORTD_PCR5
    #define CORE_PIN21_CONFIG	PORTD_PCR6
    #define CORE_PIN22_CONFIG	PORTC_PCR1
    #define CORE_PIN23_CONFIG	PORTC_PCR2
    #define CORE_PIN24_CONFIG	PORTE_PCR26
    #define CORE_PIN25_CONFIG	PORTA_PCR5
    #define CORE_PIN26_CONFIG	PORTA_PCR14
    #define CORE_PIN27_CONFIG	PORTA_PCR15
    #define CORE_PIN28_CONFIG	PORTA_PCR16
    #define CORE_PIN29_CONFIG	PORTB_PCR18
    #define CORE_PIN30_CONFIG	PORTB_PCR19
    #define CORE_PIN31_CONFIG	PORTB_PCR10
    #define CORE_PIN32_CONFIG	PORTB_PCR11
    #define CORE_PIN33_CONFIG	PORTE_PCR24
    #define CORE_PIN34_CONFIG	PORTE_PCR25
    #define CORE_PIN35_CONFIG	PORTC_PCR8
    #define CORE_PIN36_CONFIG	PORTC_PCR9
    #define CORE_PIN37_CONFIG	PORTC_PCR10
    #define CORE_PIN38_CONFIG	PORTC_PCR11
    #define CORE_PIN39_CONFIG	PORTA_PCR17
    #define CORE_PIN40_CONFIG	PORTA_PCR28
    #define CORE_PIN41_CONFIG	PORTA_PCR29
    #define CORE_PIN42_CONFIG	PORTA_PCR26
    #define CORE_PIN43_CONFIG	PORTB_PCR20
    #define CORE_PIN44_CONFIG	PORTB_PCR22
    #define CORE_PIN45_CONFIG	PORTB_PCR23
    #define CORE_PIN46_CONFIG	PORTB_PCR21
    #define CORE_PIN47_CONFIG	PORTD_PCR8
    #define CORE_PIN48_CONFIG	PORTD_PCR9
    #define CORE_PIN49_CONFIG	PORTB_PCR4
    #define CORE_PIN50_CONFIG	PORTB_PCR5
    #define CORE_PIN51_CONFIG	PORTD_PCR14
    #define CORE_PIN52_CONFIG	PORTD_PCR13
    #define CORE_PIN53_CONFIG	PORTD_PCR12
    #define CORE_PIN54_CONFIG	PORTD_PCR15
    #define CORE_PIN55_CONFIG	PORTD_PCR11
    #define CORE_PIN56_CONFIG	PORTE_PCR10
    #define CORE_PIN57_CONFIG	PORTE_PCR11
    #define CORE_PIN58_CONFIG	PORTE_PCR0
    #define CORE_PIN59_CONFIG	PORTE_PCR1
    #define CORE_PIN60_CONFIG	PORTE_PCR2
    #define CORE_PIN61_CONFIG	PORTE_PCR3
    #define CORE_PIN62_CONFIG	PORTE_PCR4
    #define CORE_PIN63_CONFIG	PORTE_PCR5
    
    #define CORE_ADC0_PIN		14
    #define CORE_ADC1_PIN		15
    #define CORE_ADC2_PIN		16
    #define CORE_ADC3_PIN		17
    #define CORE_ADC4_PIN		18
    #define CORE_ADC5_PIN		19
    #define CORE_ADC6_PIN		20
    #define CORE_ADC7_PIN		21
    #define CORE_ADC8_PIN		22
    #define CORE_ADC9_PIN		23
    #define CORE_ADC10_PIN		64
    #define CORE_ADC11_PIN		65
    #define CORE_ADC12_PIN		31
    #define CORE_ADC13_PIN		32
    #define CORE_ADC14_PIN		33
    #define CORE_ADC15_PIN		34
    #define CORE_ADC16_PIN		35
    #define CORE_ADC17_PIN		36
    #define CORE_ADC18_PIN		37
    #define CORE_ADC19_PIN		38
    #define CORE_ADC20_PIN		39
    #define CORE_ADC21_PIN		66
    #define CORE_ADC22_PIN		67
    #define CORE_ADC23_PIN		49
    #define CORE_ADC24_PIN		50
    #define CORE_ADC25_PIN		68
    #define CORE_ADC26_PIN		69
    
    #define CORE_RXD0_PIN		0
    #define CORE_TXD0_PIN		1
    #define CORE_RXD1_PIN		9
    #define CORE_TXD1_PIN		10
    #define CORE_RXD2_PIN		7
    #define CORE_TXD2_PIN		8
    #define CORE_RXD3_PIN		31
    #define CORE_TXD3_PIN		32
    #define CORE_RXD4_PIN		34
    #define CORE_TXD4_PIN		33
    
    #define CORE_INT0_PIN		0
    #define CORE_INT1_PIN		1
    #define CORE_INT2_PIN		2
    #define CORE_INT3_PIN		3
    #define CORE_INT4_PIN		4
    #define CORE_INT5_PIN		5
    #define CORE_INT6_PIN		6
    #define CORE_INT7_PIN		7
    #define CORE_INT8_PIN		8
    #define CORE_INT9_PIN		9
    #define CORE_INT10_PIN		10
    #define CORE_INT11_PIN		11
    #define CORE_INT12_PIN		12
    #define CORE_INT13_PIN		13
    #define CORE_INT14_PIN		14
    #define CORE_INT15_PIN		15
    #define CORE_INT16_PIN		16
    #define CORE_INT17_PIN		17
    #define CORE_INT18_PIN		18
    #define CORE_INT19_PIN		19
    #define CORE_INT20_PIN		20
    #define CORE_INT21_PIN		21
    #define CORE_INT22_PIN		22
    #define CORE_INT23_PIN		23
    #define CORE_INT24_PIN		24
    #define CORE_INT25_PIN		25
    #define CORE_INT26_PIN		26
    #define CORE_INT27_PIN		27
    #define CORE_INT28_PIN		28
    #define CORE_INT29_PIN		29
    #define CORE_INT30_PIN		30
    #define CORE_INT31_PIN		31
    #define CORE_INT32_PIN		32
    #define CORE_INT33_PIN		33
    #define CORE_INT34_PIN		34
    #define CORE_INT35_PIN		35
    #define CORE_INT36_PIN		36
    #define CORE_INT37_PIN		37
    #define CORE_INT38_PIN		38
    #define CORE_INT39_PIN		39
    #define CORE_INT40_PIN		40
    #define CORE_INT41_PIN		41
    #define CORE_INT42_PIN		42
    #define CORE_INT43_PIN		43
    #define CORE_INT44_PIN		44
    #define CORE_INT45_PIN		45
    #define CORE_INT46_PIN		46
    #define CORE_INT47_PIN		47
    #define CORE_INT48_PIN		48
    #define CORE_INT49_PIN		49
    #define CORE_INT50_PIN		50
    #define CORE_INT51_PIN		51
    #define CORE_INT52_PIN		52
    #define CORE_INT53_PIN		53
    #define CORE_INT54_PIN		54
    #define CORE_INT55_PIN		55
    #define CORE_INT56_PIN		56
    #define CORE_INT57_PIN		57
    #define CORE_INT58_PIN		58
    #define CORE_INT59_PIN		59
    #define CORE_INT60_PIN		60
    #define CORE_INT61_PIN		61
    #define CORE_INT62_PIN		62
    #define CORE_INT63_PIN		63
    #define CORE_INT_EVERY_PIN	1
    
    
    
    
    
    #define CORE_FTM0_CH0_PIN	22
    #define CORE_FTM0_CH1_PIN	23
    #define CORE_FTM0_CH2_PIN	 9
    #define CORE_FTM0_CH3_PIN	10
    #define CORE_FTM0_CH4_PIN	 6
    #define CORE_FTM0_CH5_PIN	20
    #define CORE_FTM0_CH6_PIN	21
    #define CORE_FTM0_CH7_PIN	 5
    #define CORE_FTM1_CH0_PIN	 3
    #define CORE_FTM1_CH1_PIN	 4
    #define CORE_FTM2_CH0_PIN	29
    #define CORE_FTM2_CH1_PIN	30
    #define CORE_FTM3_CH0_PIN	 2
    #define CORE_FTM3_CH1_PIN	14
    #define CORE_FTM3_CH2_PIN	 7
    #define CORE_FTM3_CH3_PIN	 8
    #define CORE_FTM3_CH4_PIN	35
    #define CORE_FTM3_CH5_PIN	36
    #define CORE_FTM3_CH6_PIN	37
    #define CORE_FTM3_CH7_PIN	38
    #define CORE_TPM1_CH0_PIN	16
    #define CORE_TPM1_CH1_PIN	17
    
    
    
    #ifdef __cplusplus
    extern "C" {
    #endif
    
    void digitalWrite(uint8_t pin, uint8_t val);
    static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused));
    static inline void digitalWriteFast(uint8_t pin, uint8_t val)
    {
    	if (__builtin_constant_p(pin)) {
    		if (val) {
    			if (pin == 0) {
    				CORE_PIN0_PORTSET = CORE_PIN0_BITMASK;
    			} else if (pin == 1) {
    				CORE_PIN1_PORTSET = CORE_PIN1_BITMASK;
    			} else if (pin == 2) {
    				CORE_PIN2_PORTSET = CORE_PIN2_BITMASK;
    			} else if (pin == 3) {
    				CORE_PIN3_PORTSET = CORE_PIN3_BITMASK;
    			} else if (pin == 4) {
    				CORE_PIN4_PORTSET = CORE_PIN4_BITMASK;
    			} else if (pin == 5) {
    				CORE_PIN5_PORTSET = CORE_PIN5_BITMASK;
    			} else if (pin == 6) {
    				CORE_PIN6_PORTSET = CORE_PIN6_BITMASK;
    			} else if (pin == 7) {
    				CORE_PIN7_PORTSET = CORE_PIN7_BITMASK;
    			} else if (pin == 8) {
    				CORE_PIN8_PORTSET = CORE_PIN8_BITMASK;
    			} else if (pin == 9) {
    				CORE_PIN9_PORTSET = CORE_PIN9_BITMASK;
    			} else if (pin == 10) {
    				CORE_PIN10_PORTSET = CORE_PIN10_BITMASK;
    			} else if (pin == 11) {
    				CORE_PIN11_PORTSET = CORE_PIN11_BITMASK;
    			} else if (pin == 12) {
    				CORE_PIN12_PORTSET = CORE_PIN12_BITMASK;
    			} else if (pin == 13) {
    				CORE_PIN13_PORTSET = CORE_PIN13_BITMASK;
    			} else if (pin == 14) {
    				CORE_PIN14_PORTSET = CORE_PIN14_BITMASK;
    			} else if (pin == 15) {
    				CORE_PIN15_PORTSET = CORE_PIN15_BITMASK;
    			} else if (pin == 16) {
    				CORE_PIN16_PORTSET = CORE_PIN16_BITMASK;
    			} else if (pin == 17) {
    				CORE_PIN17_PORTSET = CORE_PIN17_BITMASK;
    			} else if (pin == 18) {
    				CORE_PIN18_PORTSET = CORE_PIN18_BITMASK;
    			} else if (pin == 19) {
    				CORE_PIN19_PORTSET = CORE_PIN19_BITMASK;
    			} else if (pin == 20) {
    				CORE_PIN20_PORTSET = CORE_PIN20_BITMASK;
    			} else if (pin == 21) {
    				CORE_PIN21_PORTSET = CORE_PIN21_BITMASK;
    			} else if (pin == 22) {
    				CORE_PIN22_PORTSET = CORE_PIN22_BITMASK;
    			} else if (pin == 23) {
    				CORE_PIN23_PORTSET = CORE_PIN23_BITMASK;
    			} else if (pin == 24) {
    				CORE_PIN24_PORTSET = CORE_PIN24_BITMASK;
    			} else if (pin == 25) {
    				CORE_PIN25_PORTSET = CORE_PIN25_BITMASK;
    			} else if (pin == 26) {
    				CORE_PIN26_PORTSET = CORE_PIN26_BITMASK;
    			}
    			#if defined(CORE_PIN27_PORTSET)
    			  else if (pin == 27) {
    				CORE_PIN27_PORTSET = CORE_PIN27_BITMASK;
    			} else if (pin == 28) {
    				CORE_PIN28_PORTSET = CORE_PIN28_BITMASK;
    			} else if (pin == 29) {
    				CORE_PIN29_PORTSET = CORE_PIN29_BITMASK;
    			} else if (pin == 30) {
    				CORE_PIN30_PORTSET = CORE_PIN30_BITMASK;
    			} else if (pin == 31) {
    				CORE_PIN31_PORTSET = CORE_PIN31_BITMASK;
    			} else if (pin == 32) {
    				CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;
    			} else if (pin == 33) {
    				CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;
    			}
    			#endif
    			#if defined(CORE_PIN34_PORTSET)
    			  else if (pin == 34) {
    				CORE_PIN34_PORTSET = CORE_PIN34_BITMASK;
    			} else if (pin == 35) {
    				CORE_PIN35_PORTSET = CORE_PIN35_BITMASK;
    			} else if (pin == 36) {
    				CORE_PIN36_PORTSET = CORE_PIN36_BITMASK;
    			} else if (pin == 37) {
    				CORE_PIN37_PORTSET = CORE_PIN37_BITMASK;
    			} else if (pin == 38) {
    				CORE_PIN38_PORTSET = CORE_PIN38_BITMASK;
    			} else if (pin == 39) {
    				CORE_PIN39_PORTSET = CORE_PIN39_BITMASK;
    			} else if (pin == 40) {
    				CORE_PIN40_PORTSET = CORE_PIN40_BITMASK;
    			} else if (pin == 41) {
    				CORE_PIN41_PORTSET = CORE_PIN41_BITMASK;
    			} else if (pin == 42) {
    				CORE_PIN42_PORTSET = CORE_PIN42_BITMASK;
    			} else if (pin == 43) {
    				CORE_PIN43_PORTSET = CORE_PIN43_BITMASK;
    			} else if (pin == 44) {
    				CORE_PIN44_PORTSET = CORE_PIN44_BITMASK;
    			} else if (pin == 45) {
    				CORE_PIN45_PORTSET = CORE_PIN45_BITMASK;
    			} else if (pin == 46) {
    				CORE_PIN46_PORTSET = CORE_PIN46_BITMASK;
    			} else if (pin == 47) {
    				CORE_PIN47_PORTSET = CORE_PIN47_BITMASK;
    			} else if (pin == 48) {
    				CORE_PIN48_PORTSET = CORE_PIN48_BITMASK;
    			} else if (pin == 49) {
    				CORE_PIN49_PORTSET = CORE_PIN49_BITMASK;
    			} else if (pin == 50) {
    				CORE_PIN50_PORTSET = CORE_PIN50_BITMASK;
    			} else if (pin == 51) {
    				CORE_PIN51_PORTSET = CORE_PIN51_BITMASK;
    			} else if (pin == 52) {
    				CORE_PIN52_PORTSET = CORE_PIN52_BITMASK;
    			} else if (pin == 53) {
    				CORE_PIN53_PORTSET = CORE_PIN53_BITMASK;
    			} else if (pin == 54) {
    				CORE_PIN54_PORTSET = CORE_PIN54_BITMASK;
    			} else if (pin == 55) {
    				CORE_PIN55_PORTSET = CORE_PIN55_BITMASK;
    			} else if (pin == 56) {
    				CORE_PIN56_PORTSET = CORE_PIN56_BITMASK;
    			} else if (pin == 57) {
    				CORE_PIN57_PORTSET = CORE_PIN57_BITMASK;
    			} else if (pin == 58) {
    				CORE_PIN58_PORTSET = CORE_PIN58_BITMASK;
    			} else if (pin == 59) {
    				CORE_PIN59_PORTSET = CORE_PIN59_BITMASK;
    			} else if (pin == 60) {
    				CORE_PIN60_PORTSET = CORE_PIN60_BITMASK;
    			} else if (pin == 61) {
    				CORE_PIN61_PORTSET = CORE_PIN61_BITMASK;
    			} else if (pin == 62) {
    				CORE_PIN62_PORTSET = CORE_PIN62_BITMASK;
    			} else if (pin == 63) {
    				CORE_PIN63_PORTSET = CORE_PIN63_BITMASK;
    			}
    			#ifdef TEENSY_3_6_PRO
    			else if (pin == 72) {
    				CORE_PIN72_PORTSET = CORE_PIN72_BITMASK;
    			} else if (pin == 73) {
    				CORE_PIN73_PORTSET = CORE_PIN73_BITMASK;
    			} else if (pin == 74) {
    				CORE_PIN74_PORTSET = CORE_PIN74_BITMASK;
    			} else if (pin == 75) {
    				CORE_PIN75_PORTSET = CORE_PIN75_BITMASK;
    			} else if (pin == 76) {
    				CORE_PIN76_PORTSET = CORE_PIN76_BITMASK;
    			} else if (pin == 77) {
    				CORE_PIN77_PORTSET = CORE_PIN77_BITMASK;
    			} else if (pin == 78) {
    				CORE_PIN78_PORTSET = CORE_PIN78_BITMASK;
    			} else if (pin == 79) {
    				CORE_PIN79_PORTSET = CORE_PIN79_BITMASK;
    			} else if (pin == 80) {
    				CORE_PIN80_PORTSET = CORE_PIN80_BITMASK;
    			} else if (pin == 81) {
    				CORE_PIN81_PORTSET = CORE_PIN81_BITMASK;
    			} else if (pin == 82) {
    				CORE_PIN82_PORTSET = CORE_PIN82_BITMASK;
    			} else if (pin == 83) {
    				CORE_PIN83_PORTSET = CORE_PIN83_BITMASK;
    			} else if (pin == 84) {
    				CORE_PIN84_PORTSET = CORE_PIN84_BITMASK;
    			} else if (pin == 85) {
    				CORE_PIN85_PORTSET = CORE_PIN85_BITMASK;
    			} else if (pin == 86) {
    				CORE_PIN86_PORTSET = CORE_PIN86_BITMASK;
    			} else if (pin == 87) {
    				CORE_PIN87_PORTSET = CORE_PIN87_BITMASK;
    			} else if (pin == 88) {
    				CORE_PIN88_PORTSET = CORE_PIN88_BITMASK;
    			} else if (pin == 89) {
    				CORE_PIN89_PORTSET = CORE_PIN89_BITMASK;
    			} else if (pin == 90) {
    				CORE_PIN90_PORTSET = CORE_PIN90_BITMASK;
    			} else if (pin == 91) {
    				CORE_PIN91_PORTSET = CORE_PIN91_BITMASK;
    			} else if (pin == 92) {
    				CORE_PIN92_PORTSET = CORE_PIN92_BITMASK;
    			} else if (pin == 93) {
    				CORE_PIN93_PORTSET = CORE_PIN93_BITMASK;
    			} else if (pin == 94) {
    				CORE_PIN94_PORTSET = CORE_PIN94_BITMASK;
    			} else if (pin == 95) {
    				CORE_PIN95_PORTSET = CORE_PIN95_BITMASK;
    			} else if (pin == 96) {
    				CORE_PIN96_PORTSET = CORE_PIN96_BITMASK;
    			} else if (pin == 97) {
    				CORE_PIN97_PORTSET = CORE_PIN97_BITMASK;
    			} else if (pin == 98) {
    				CORE_PIN98_PORTSET = CORE_PIN98_BITMASK;
    			} else if (pin == 99) {
    				CORE_PIN99_PORTSET = CORE_PIN99_BITMASK;
    			}
    			#endif
    			#endif
    		} else {
    			if (pin == 0) {
    				CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;
    			} else if (pin == 1) {
    				CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK;
    			} else if (pin == 2) {
    				CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK;
    			} else if (pin == 3) {
    				CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK;
    			} else if (pin == 4) {
    				CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK;
    			} else if (pin == 5) {
    				CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK;
    			} else if (pin == 6) {
    				CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK;
    			} else if (pin == 7) {
    				CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK;
    			} else if (pin == 8) {
    				CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK;
    			} else if (pin == 9) {
    				CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK;
    			} else if (pin == 10) {
    				CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK;
    			} else if (pin == 11) {
    				CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK;
    			} else if (pin == 12) {
    				CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK;
    			} else if (pin == 13) {
    				CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK;
    			} else if (pin == 14) {
    				CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK;
    			} else if (pin == 15) {
    				CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK;
    			} else if (pin == 16) {
    				CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK;
    			} else if (pin == 17) {
    				CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK;
    			} else if (pin == 18) {
    				CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK;
    			} else if (pin == 19) {
    				CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK;
    			} else if (pin == 20) {
    				CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK;
    			} else if (pin == 21) {
    				CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK;
    			} else if (pin == 22) {
    				CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK;
    			} else if (pin == 23) {
    				CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK;
    			} else if (pin == 24) {
    				CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK;
    			} else if (pin == 25) {
    				CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK;
    			} else if (pin == 26) {
    				CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK;
    			}
    			#if defined(CORE_PIN27_PORTCLEAR)
    			  else if (pin == 27) {
    				CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK;
    			} else if (pin == 28) {
    				CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK;
    			} else if (pin == 29) {
    				CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK;
    			} else if (pin == 30) {
    				CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK;
    			} else if (pin == 31) {
    				CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK;
    			} else if (pin == 32) {
    				CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;
    			} else if (pin == 33) {
    				CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;
    			}
    			#endif
    			#if defined(CORE_PIN34_PORTCLEAR)
    			  else if (pin == 34) {
    				CORE_PIN34_PORTCLEAR = CORE_PIN34_BITMASK;
    			} else if (pin == 35) {
    				CORE_PIN35_PORTCLEAR = CORE_PIN35_BITMASK;
    			} else if (pin == 36) {
    				CORE_PIN36_PORTCLEAR = CORE_PIN36_BITMASK;
    			} else if (pin == 37) {
    				CORE_PIN37_PORTCLEAR = CORE_PIN37_BITMASK;
    			} else if (pin == 38) {
    				CORE_PIN38_PORTCLEAR = CORE_PIN38_BITMASK;
    			} else if (pin == 39) {
    				CORE_PIN39_PORTCLEAR = CORE_PIN39_BITMASK;
    			} else if (pin == 40) {
    				CORE_PIN40_PORTCLEAR = CORE_PIN40_BITMASK;
    			} else if (pin == 41) {
    				CORE_PIN41_PORTCLEAR = CORE_PIN41_BITMASK;
    			} else if (pin == 42) {
    				CORE_PIN42_PORTCLEAR = CORE_PIN42_BITMASK;
    			} else if (pin == 43) {
    				CORE_PIN43_PORTCLEAR = CORE_PIN43_BITMASK;
    			} else if (pin == 44) {
    				CORE_PIN44_PORTCLEAR = CORE_PIN44_BITMASK;
    			} else if (pin == 45) {
    				CORE_PIN45_PORTCLEAR = CORE_PIN45_BITMASK;
    			} else if (pin == 46) {
    				CORE_PIN46_PORTCLEAR = CORE_PIN46_BITMASK;
    			} else if (pin == 47) {
    				CORE_PIN47_PORTCLEAR = CORE_PIN47_BITMASK;
    			} else if (pin == 48) {
    				CORE_PIN48_PORTCLEAR = CORE_PIN48_BITMASK;
    			} else if (pin == 49) {
    				CORE_PIN49_PORTCLEAR = CORE_PIN49_BITMASK;
    			} else if (pin == 50) {
    				CORE_PIN50_PORTCLEAR = CORE_PIN50_BITMASK;
    			} else if (pin == 51) {
    				CORE_PIN51_PORTCLEAR = CORE_PIN51_BITMASK;
    			} else if (pin == 52) {
    				CORE_PIN52_PORTCLEAR = CORE_PIN52_BITMASK;
    			} else if (pin == 53) {
    				CORE_PIN53_PORTCLEAR = CORE_PIN53_BITMASK;
    			} else if (pin == 54) {
    				CORE_PIN54_PORTCLEAR = CORE_PIN54_BITMASK;
    			} else if (pin == 55) {
    				CORE_PIN55_PORTCLEAR = CORE_PIN55_BITMASK;
    			} else if (pin == 56) {
    				CORE_PIN56_PORTCLEAR = CORE_PIN56_BITMASK;
    			} else if (pin == 57) {
    				CORE_PIN57_PORTCLEAR = CORE_PIN57_BITMASK;
    			} else if (pin == 58) {
    				CORE_PIN58_PORTCLEAR = CORE_PIN58_BITMASK;
    			} else if (pin == 59) {
    				CORE_PIN59_PORTCLEAR = CORE_PIN59_BITMASK;
    			} else if (pin == 60) {
    				CORE_PIN60_PORTCLEAR = CORE_PIN60_BITMASK;
    			} else if (pin == 61) {
    				CORE_PIN61_PORTCLEAR = CORE_PIN61_BITMASK;
    			} else if (pin == 62) {
    				CORE_PIN62_PORTCLEAR = CORE_PIN62_BITMASK;
    			} else if (pin == 63) {
    				CORE_PIN63_PORTCLEAR = CORE_PIN63_BITMASK;
    			}
    			#ifdef TEENSY_3_6_PRO
    			else if (pin == 72) {
    				CORE_PIN72_PORTCLEAR = CORE_PIN72_BITMASK;
    			} else if (pin == 73) {
    				CORE_PIN73_PORTCLEAR = CORE_PIN73_BITMASK;
    			} else if (pin == 74) {
    				CORE_PIN74_PORTCLEAR = CORE_PIN74_BITMASK;
    			} else if (pin == 75) {
    				CORE_PIN75_PORTCLEAR = CORE_PIN75_BITMASK;
    			} else if (pin == 76) {
    				CORE_PIN76_PORTCLEAR = CORE_PIN76_BITMASK;
    			} else if (pin == 77) {
    				CORE_PIN77_PORTCLEAR = CORE_PIN77_BITMASK;
    			} else if (pin == 78) {
    				CORE_PIN78_PORTCLEAR = CORE_PIN78_BITMASK;
    			} else if (pin == 79) {
    				CORE_PIN79_PORTCLEAR = CORE_PIN79_BITMASK;
    			} else if (pin == 80) {
    				CORE_PIN80_PORTCLEAR = CORE_PIN80_BITMASK;
    			} else if (pin == 81) {
    				CORE_PIN81_PORTCLEAR = CORE_PIN81_BITMASK;
    			} else if (pin == 82) {
    				CORE_PIN82_PORTCLEAR = CORE_PIN82_BITMASK;
    			} else if (pin == 83) {
    				CORE_PIN83_PORTCLEAR = CORE_PIN83_BITMASK;
    			} else if (pin == 84) {
    				CORE_PIN84_PORTCLEAR = CORE_PIN84_BITMASK;
    			} else if (pin == 85) {
    				CORE_PIN85_PORTCLEAR = CORE_PIN85_BITMASK;
    			} else if (pin == 86) {
    				CORE_PIN86_PORTCLEAR = CORE_PIN86_BITMASK;
    			} else if (pin == 87) {
    				CORE_PIN87_PORTCLEAR = CORE_PIN87_BITMASK;
    			} else if (pin == 88) {
    				CORE_PIN88_PORTCLEAR = CORE_PIN88_BITMASK;
    			} else if (pin == 89) {
    				CORE_PIN89_PORTCLEAR = CORE_PIN89_BITMASK;
    			} else if (pin == 90) {
    				CORE_PIN90_PORTCLEAR = CORE_PIN90_BITMASK;
    			} else if (pin == 91) {
    				CORE_PIN91_PORTCLEAR = CORE_PIN91_BITMASK;
    			} else if (pin == 92) {
    				CORE_PIN92_PORTCLEAR = CORE_PIN92_BITMASK;
    			} else if (pin == 93) {
    				CORE_PIN93_PORTCLEAR = CORE_PIN93_BITMASK;
    			} else if (pin == 94) {
    				CORE_PIN94_PORTCLEAR = CORE_PIN94_BITMASK;
    			} else if (pin == 95) {
    				CORE_PIN95_PORTCLEAR = CORE_PIN95_BITMASK;
    			} else if (pin == 96) {
    				CORE_PIN96_PORTCLEAR = CORE_PIN96_BITMASK;
    			} else if (pin == 97) {
    				CORE_PIN97_PORTCLEAR = CORE_PIN97_BITMASK;
    			} else if (pin == 98) {
    				CORE_PIN98_PORTCLEAR = CORE_PIN98_BITMASK;
    			} else if (pin == 99) {
    				CORE_PIN99_PORTCLEAR = CORE_PIN99_BITMASK;
    			}
    			#endif
    			#endif
    		}
    	} else {
    		if (val) {
    			*portSetRegister(pin) = digitalPinToBitMask(pin);
    		} else {
    			*portClearRegister(pin) = digitalPinToBitMask(pin);
    		}
    	}
    }
    
    uint8_t digitalRead(uint8_t pin);
    static inline uint8_t digitalReadFast(uint8_t pin) __attribute__((always_inline, unused));
    static inline uint8_t digitalReadFast(uint8_t pin)
    {
    	if (__builtin_constant_p(pin)) {
    		if (pin == 0) {
    			return (CORE_PIN0_PINREG & CORE_PIN0_BITMASK) ? 1 : 0;
    		} else if (pin == 1) {
    			return (CORE_PIN1_PINREG & CORE_PIN1_BITMASK) ? 1 : 0;
    		} else if (pin == 2) {
    			return (CORE_PIN2_PINREG & CORE_PIN2_BITMASK) ? 1 : 0;
    		} else if (pin == 3) {
    			return (CORE_PIN3_PINREG & CORE_PIN3_BITMASK) ? 1 : 0;
    		} else if (pin == 4) {
    			return (CORE_PIN4_PINREG & CORE_PIN4_BITMASK) ? 1 : 0;
    		} else if (pin == 5) {
    			return (CORE_PIN5_PINREG & CORE_PIN5_BITMASK) ? 1 : 0;
    		} else if (pin == 6) {
    			return (CORE_PIN6_PINREG & CORE_PIN6_BITMASK) ? 1 : 0;
    		} else if (pin == 7) {
    			return (CORE_PIN7_PINREG & CORE_PIN7_BITMASK) ? 1 : 0;
    		} else if (pin == 8) {
    			return (CORE_PIN8_PINREG & CORE_PIN8_BITMASK) ? 1 : 0;
    		} else if (pin == 9) {
    			return (CORE_PIN9_PINREG & CORE_PIN9_BITMASK) ? 1 : 0;
    		} else if (pin == 10) {
    			return (CORE_PIN10_PINREG & CORE_PIN10_BITMASK) ? 1 : 0;
    		} else if (pin == 11) {
    			return (CORE_PIN11_PINREG & CORE_PIN11_BITMASK) ? 1 : 0;
    		} else if (pin == 12) {
    			return (CORE_PIN12_PINREG & CORE_PIN12_BITMASK) ? 1 : 0;
    		} else if (pin == 13) {
    			return (CORE_PIN13_PINREG & CORE_PIN13_BITMASK) ? 1 : 0;
    		} else if (pin == 14) {
    			return (CORE_PIN14_PINREG & CORE_PIN14_BITMASK) ? 1 : 0;
    		} else if (pin == 15) {
    			return (CORE_PIN15_PINREG & CORE_PIN15_BITMASK) ? 1 : 0;
    		} else if (pin == 16) {
    			return (CORE_PIN16_PINREG & CORE_PIN16_BITMASK) ? 1 : 0;
    		} else if (pin == 17) {
    			return (CORE_PIN17_PINREG & CORE_PIN17_BITMASK) ? 1 : 0;
    		} else if (pin == 18) {
    			return (CORE_PIN18_PINREG & CORE_PIN18_BITMASK) ? 1 : 0;
    		} else if (pin == 19) {
    			return (CORE_PIN19_PINREG & CORE_PIN19_BITMASK) ? 1 : 0;
    		} else if (pin == 20) {
    			return (CORE_PIN20_PINREG & CORE_PIN20_BITMASK) ? 1 : 0;
    		} else if (pin == 21) {
    			return (CORE_PIN21_PINREG & CORE_PIN21_BITMASK) ? 1 : 0;
    		} else if (pin == 22) {
    			return (CORE_PIN22_PINREG & CORE_PIN22_BITMASK) ? 1 : 0;
    		} else if (pin == 23) {
    			return (CORE_PIN23_PINREG & CORE_PIN23_BITMASK) ? 1 : 0;
    		} else if (pin == 24) {
    			return (CORE_PIN24_PINREG & CORE_PIN24_BITMASK) ? 1 : 0;
    		} else if (pin == 25) {
    			return (CORE_PIN25_PINREG & CORE_PIN25_BITMASK) ? 1 : 0;
    		} else if (pin == 26) {
    			return (CORE_PIN26_PINREG & CORE_PIN26_BITMASK) ? 1 : 0;
    		}
    		#if defined(CORE_PIN27_PINREG)
    		  else if (pin == 27) {
    			return (CORE_PIN27_PINREG & CORE_PIN27_BITMASK) ? 1 : 0;
    		} else if (pin == 28) {
    			return (CORE_PIN28_PINREG & CORE_PIN28_BITMASK) ? 1 : 0;
    		} else if (pin == 29) {
    			return (CORE_PIN29_PINREG & CORE_PIN29_BITMASK) ? 1 : 0;
    		} else if (pin == 30) {
    			return (CORE_PIN30_PINREG & CORE_PIN30_BITMASK) ? 1 : 0;
    		} else if (pin == 31) {
    			return (CORE_PIN31_PINREG & CORE_PIN31_BITMASK) ? 1 : 0;
    		} else if (pin == 32) {
    			return (CORE_PIN32_PINREG & CORE_PIN32_BITMASK) ? 1 : 0;
    		} else if (pin == 33) {
    			return (CORE_PIN33_PINREG & CORE_PIN33_BITMASK) ? 1 : 0;
    		}
    		#endif
    		#if defined(CORE_PIN34_PINREG)
    		  else if (pin == 34) {
    			return (CORE_PIN34_PINREG & CORE_PIN34_BITMASK) ? 1 : 0;
    		} else if (pin == 35) {
    			return (CORE_PIN35_PINREG & CORE_PIN35_BITMASK) ? 1 : 0;
    		} else if (pin == 36) {
    			return (CORE_PIN36_PINREG & CORE_PIN36_BITMASK) ? 1 : 0;
    		} else if (pin == 37) {
    			return (CORE_PIN37_PINREG & CORE_PIN37_BITMASK) ? 1 : 0;
    		} else if (pin == 38) {
    			return (CORE_PIN38_PINREG & CORE_PIN38_BITMASK) ? 1 : 0;
    		} else if (pin == 39) {
    			return (CORE_PIN39_PINREG & CORE_PIN39_BITMASK) ? 1 : 0;
    		} else if (pin == 40) {
    			return (CORE_PIN40_PINREG & CORE_PIN40_BITMASK) ? 1 : 0;
    		} else if (pin == 41) {
    			return (CORE_PIN41_PINREG & CORE_PIN41_BITMASK) ? 1 : 0;
    		} else if (pin == 42) {
    			return (CORE_PIN42_PINREG & CORE_PIN42_BITMASK) ? 1 : 0;
    		} else if (pin == 43) {
    			return (CORE_PIN43_PINREG & CORE_PIN43_BITMASK) ? 1 : 0;
    		} else if (pin == 44) {
    			return (CORE_PIN44_PINREG & CORE_PIN44_BITMASK) ? 1 : 0;
    		} else if (pin == 45) {
    			return (CORE_PIN45_PINREG & CORE_PIN45_BITMASK) ? 1 : 0;
    		} else if (pin == 46) {
    			return (CORE_PIN46_PINREG & CORE_PIN46_BITMASK) ? 1 : 0;
    		} else if (pin == 47) {
    			return (CORE_PIN47_PINREG & CORE_PIN47_BITMASK) ? 1 : 0;
    		} else if (pin == 48) {
    			return (CORE_PIN48_PINREG & CORE_PIN48_BITMASK) ? 1 : 0;
    		} else if (pin == 49) {
    			return (CORE_PIN49_PINREG & CORE_PIN49_BITMASK) ? 1 : 0;
    		} else if (pin == 50) {
    			return (CORE_PIN50_PINREG & CORE_PIN50_BITMASK) ? 1 : 0;
    		} else if (pin == 51) {
    			return (CORE_PIN51_PINREG & CORE_PIN51_BITMASK) ? 1 : 0;
    		} else if (pin == 52) {
    			return (CORE_PIN52_PINREG & CORE_PIN52_BITMASK) ? 1 : 0;
    		} else if (pin == 53) {
    			return (CORE_PIN53_PINREG & CORE_PIN53_BITMASK) ? 1 : 0;
    		} else if (pin == 54) {
    			return (CORE_PIN54_PINREG & CORE_PIN54_BITMASK) ? 1 : 0;
    		} else if (pin == 55) {
    			return (CORE_PIN55_PINREG & CORE_PIN55_BITMASK) ? 1 : 0;
    		} else if (pin == 56) {
    			return (CORE_PIN56_PINREG & CORE_PIN56_BITMASK) ? 1 : 0;
    		} else if (pin == 57) {
    			return (CORE_PIN57_PINREG & CORE_PIN57_BITMASK) ? 1 : 0;
    		} else if (pin == 58) {
    			return (CORE_PIN58_PINREG & CORE_PIN58_BITMASK) ? 1 : 0;
    		} else if (pin == 59) {
    			return (CORE_PIN59_PINREG & CORE_PIN59_BITMASK) ? 1 : 0;
    		} else if (pin == 60) {
    			return (CORE_PIN60_PINREG & CORE_PIN60_BITMASK) ? 1 : 0;
    		} else if (pin == 61) {
    			return (CORE_PIN61_PINREG & CORE_PIN61_BITMASK) ? 1 : 0;
    		} else if (pin == 62) {
    			return (CORE_PIN62_PINREG & CORE_PIN62_BITMASK) ? 1 : 0;
    		} else if (pin == 63) {
    			return (CORE_PIN63_PINREG & CORE_PIN63_BITMASK) ? 1 : 0;
    		}
    		#ifdef TEENSY_3_6_PRO
    		else if (pin == 72) {
    			return (CORE_PIN72_PINREG & CORE_PIN72_BITMASK) ? 1 : 0;
    		} else if (pin == 73) {
    			return (CORE_PIN73_PINREG & CORE_PIN73_BITMASK) ? 1 : 0;
    		} else if (pin == 74) {
    			return (CORE_PIN74_PINREG & CORE_PIN74_BITMASK) ? 1 : 0;
    		} else if (pin == 75) {
    			return (CORE_PIN75_PINREG & CORE_PIN75_BITMASK) ? 1 : 0;
    		} else if (pin == 76) {
    			return (CORE_PIN76_PINREG & CORE_PIN76_BITMASK) ? 1 : 0;
    		} else if (pin == 77) {
    			return (CORE_PIN77_PINREG & CORE_PIN77_BITMASK) ? 1 : 0;
    		} else if (pin == 78) {
    			return (CORE_PIN78_PINREG & CORE_PIN78_BITMASK) ? 1 : 0;
    		} else if (pin == 79) {
    			return (CORE_PIN79_PINREG & CORE_PIN79_BITMASK) ? 1 : 0;
    		} else if (pin == 80) {
    			return (CORE_PIN80_PINREG & CORE_PIN80_BITMASK) ? 1 : 0;
    		} else if (pin == 81) {
    			return (CORE_PIN81_PINREG & CORE_PIN81_BITMASK) ? 1 : 0;
    		} else if (pin == 82) {
    			return (CORE_PIN82_PINREG & CORE_PIN82_BITMASK) ? 1 : 0;
    		} else if (pin == 83) {
    			return (CORE_PIN83_PINREG & CORE_PIN83_BITMASK) ? 1 : 0;
    		} else if (pin == 84) {
    			return (CORE_PIN84_PINREG & CORE_PIN84_BITMASK) ? 1 : 0;
    		} else if (pin == 85) {
    			return (CORE_PIN85_PINREG & CORE_PIN85_BITMASK) ? 1 : 0;
    		} else if (pin == 86) {
    			return (CORE_PIN86_PINREG & CORE_PIN86_BITMASK) ? 1 : 0;
    		} else if (pin == 87) {
    			return (CORE_PIN87_PINREG & CORE_PIN87_BITMASK) ? 1 : 0;
    		} else if (pin == 88) {
    			return (CORE_PIN88_PINREG & CORE_PIN88_BITMASK) ? 1 : 0;
    		} else if (pin == 89) {
    			return (CORE_PIN89_PINREG & CORE_PIN89_BITMASK) ? 1 : 0;
    		} else if (pin == 90) {
    			return (CORE_PIN90_PINREG & CORE_PIN90_BITMASK) ? 1 : 0;
    		} else if (pin == 91) {
    			return (CORE_PIN91_PINREG & CORE_PIN91_BITMASK) ? 1 : 0;
    		} else if (pin == 92) {
    			return (CORE_PIN92_PINREG & CORE_PIN92_BITMASK) ? 1 : 0;
    		} else if (pin == 93) {
    			return (CORE_PIN93_PINREG & CORE_PIN93_BITMASK) ? 1 : 0;
    		} else if (pin == 94) {
    			return (CORE_PIN94_PINREG & CORE_PIN94_BITMASK) ? 1 : 0;
    		} else if (pin == 95) {
    			return (CORE_PIN95_PINREG & CORE_PIN95_BITMASK) ? 1 : 0;
    		} else if (pin == 96) {
    			return (CORE_PIN96_PINREG & CORE_PIN96_BITMASK) ? 1 : 0;
    		} else if (pin == 97) {
    			return (CORE_PIN97_PINREG & CORE_PIN97_BITMASK) ? 1 : 0;
    		} else if (pin == 98) {
    			return (CORE_PIN98_PINREG & CORE_PIN98_BITMASK) ? 1 : 0;
    		} else if (pin == 99) {
    			return (CORE_PIN99_PINREG & CORE_PIN99_BITMASK) ? 1 : 0;
    		}
    		#endif
    		#endif
    		  else {
    			return 0;
    		}
    	} else {
    		#if defined(KINETISK)
    		return *portInputRegister(pin);
    		#else
    		return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0;
    		#endif
    	}
    }
    
    
    void pinMode(uint8_t pin, uint8_t mode);
    void init_pins(void);
    void analogWrite(uint8_t pin, int val);
    uint32_t analogWriteRes(uint32_t bits);
    static inline uint32_t analogWriteResolution(uint32_t bits) { return analogWriteRes(bits); }
    void analogWriteFrequency(uint8_t pin, float frequency);
    void analogWriteDAC0(int val);
    void analogWriteDAC1(int val);
    #ifdef __cplusplus
    void attachInterruptVector(IRQ_NUMBER_t irq, void (*function)(void));
    #else
    void attachInterruptVector(enum IRQ_NUMBER_t irq, void (*function)(void));
    #endif
    void attachInterrupt(uint8_t pin, void (*function)(void), int mode);
    void detachInterrupt(uint8_t pin);
    void _init_Teensyduino_internal_(void);
    
    int analogRead(uint8_t pin);
    void analogReference(uint8_t type);
    void analogReadRes(unsigned int bits);
    static inline void analogReadResolution(unsigned int bits) { analogReadRes(bits); }
    void analogReadAveraging(unsigned int num);
    void analog_init(void);
    
    
    
    #define DEFAULT         0
    #define INTERNAL        2
    #define INTERNAL1V2     2
    #define INTERNAL1V1     2
    #define EXTERNAL        0
    
    
    
    
    int touchRead(uint8_t pin);
    
    
    static inline void shiftOut(uint8_t, uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));
    extern void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value) __attribute__((noinline));
    extern void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));
    extern void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value) __attribute__((noinline));
    
    static inline void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)
    {
            if (__builtin_constant_p(bitOrder)) {
                    if (bitOrder == LSBFIRST) {
                            shiftOut_lsbFirst(dataPin, clockPin, value);
                    } else {
                            shiftOut_msbFirst(dataPin, clockPin, value);
                    }
            } else {
                    _shiftOut(dataPin, clockPin, bitOrder, value);
            }
    }
    
    static inline uint8_t shiftIn(uint8_t, uint8_t, uint8_t) __attribute__((always_inline, unused));
    extern uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) __attribute__((noinline));
    extern uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));
    extern uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin) __attribute__((noinline));
    
    static inline uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)
    {
            if (__builtin_constant_p(bitOrder)) {
                    if (bitOrder == LSBFIRST) {
                            return shiftIn_lsbFirst(dataPin, clockPin);
                    } else {
                            return shiftIn_msbFirst(dataPin, clockPin);
                    }
            } else {
                    return _shiftIn(dataPin, clockPin, bitOrder);
            }
    }
    
    void _reboot_Teensyduino_(void) __attribute__((noreturn));
    void _restart_Teensyduino_(void) __attribute__((noreturn));
    
    void yield(void);
    
    void delay(uint32_t msec);
    
    extern volatile uint32_t systick_millis_count;
    
    static inline uint32_t millis(void) __attribute__((always_inline, unused));
    static inline uint32_t millis(void)
    {
    	// Reading a volatile variable to another volatile
    	// seems redundant, but isn't for some cases.
    	// Eventually this should probably be replaced by a
    	// proper memory barrier or other technique.  Please
    	// do not remove this "redundant" code without
    	// carefully verifying the case mentioned here:
    	//
    	// https://forum.pjrc.com/threads/17469-millis%28%29-on-teensy-3?p=104924&viewfull=1#post104924
    	//
    	volatile uint32_t ret = systick_millis_count; // single aligned 32 bit is atomic
    	return ret;
    }
    
    uint32_t micros(void);
    
    static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));
    static inline void delayMicroseconds(uint32_t usec)
    {
    #if F_CPU == 240000000
    	uint32_t n = usec * 80;
    #elif F_CPU == 216000000
    	uint32_t n = usec * 72;
    #elif F_CPU == 192000000
    	uint32_t n = usec * 64;
    #elif F_CPU == 180000000
    	uint32_t n = usec * 60;
    #elif F_CPU == 168000000
    	uint32_t n = usec * 56;
    #elif F_CPU == 144000000
    	uint32_t n = usec * 48;
    #elif F_CPU == 120000000
    	uint32_t n = usec * 40;
    #elif F_CPU == 96000000
    	uint32_t n = usec << 5;
    #elif F_CPU == 72000000
    	uint32_t n = usec * 24;
    #elif F_CPU == 48000000
    	uint32_t n = usec << 4;
    #elif F_CPU == 24000000
    	uint32_t n = usec << 3;
    #elif F_CPU == 16000000
    	uint32_t n = usec << 2;
    #elif F_CPU == 8000000
    	uint32_t n = usec << 1;
    #elif F_CPU == 4000000
    	uint32_t n = usec;
    #elif F_CPU == 2000000
    	uint32_t n = usec >> 1;
    #endif
        // changed because a delay of 1 micro Sec @ 2MHz will be 0
    	if (n == 0) return;
    	__asm__ volatile(
    		"L_%=_delayMicroseconds:"		"\n\t"
    #if F_CPU < 24000000
    		"nop"					"\n\t"
    #endif
    #ifdef KINETISL
    		"sub    %0, #1"				"\n\t"
    #else
    		"subs   %0, #1"				"\n\t"
    #endif
    		"bne    L_%=_delayMicroseconds"		"\n"
    		: "+r" (n) :
    	);
    }
    
    #ifdef __cplusplus
    }
    #endif
    
    
    
    
    
    
    
    
    #ifdef __cplusplus
    extern "C" {
    #endif
    unsigned long rtc_get(void);
    void rtc_set(unsigned long t);
    void rtc_compensate(int adjust);
    #ifdef __cplusplus
    }
    class teensy3_clock_class
    {
    public:
    	static unsigned long get(void) __attribute__((always_inline)) { return rtc_get(); }
    	static void set(unsigned long t) __attribute__((always_inline)) { rtc_set(t); }
    	static void compensate(int adj) __attribute__((always_inline)) { rtc_compensate(adj); }
    };
    extern teensy3_clock_class Teensy3Clock;
    #endif
    
    
    
    
    #endif
    pins_teensy.c
    Code:
    /* Teensyduino Core Library
     * http://www.pjrc.com/teensy/
     * Copyright (c) 2017 PJRC.COM, LLC.
     *
     * Permission is hereby granted, free of charge, to any person obtaining
     * a copy of this software and associated documentation files (the
     * "Software"), to deal in the Software without restriction, including
     * without limitation the rights to use, copy, modify, merge, publish,
     * distribute, sublicense, and/or sell copies of the Software, and to
     * permit persons to whom the Software is furnished to do so, subject to
     * the following conditions:
     *
     * 1. The above copyright notice and this permission notice shall be
     * included in all copies or substantial portions of the Software.
     *
     * 2. If the Software is incorporated into a build system that allows
     * selection among a list of target devices, then similar target
     * devices manufactured by PJRC.COM must be included in the list of
     * target devices and selectable in the same manner.
     *
     * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     * SOFTWARE.
     */
    
    #include "core_pins.h"
    #include "pins_arduino.h"
    #include "HardwareSerial.h"
    
    #define TEENSY_3_6_PRO  // Enable extended pin numbering scheme for custom boards; see https://forum.pjrc.com/threads/54114-Extended-Pin-Numbering?p=198761&posted=1
    
    
    #if defined(KINETISK)
    #define GPIO_BITBAND_ADDR(reg, bit) (((uint32_t)&(reg) - 0x40000000) * 32 + (bit) * 4 + 0x42000000)
    #define GPIO_BITBAND_PTR(reg, bit) ((uint32_t *)GPIO_BITBAND_ADDR((reg), (bit)))
    //#define GPIO_SET_BIT(reg, bit) (*GPIO_BITBAND_PTR((reg), (bit)) = 1)
    //#define GPIO_CLR_BIT(reg, bit) (*GPIO_BITBAND_PTR((reg), (bit)) = 0)
    const struct digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM[] = {
    	{GPIO_BITBAND_PTR(CORE_PIN0_PORTREG, CORE_PIN0_BIT), &CORE_PIN0_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN1_PORTREG, CORE_PIN1_BIT), &CORE_PIN1_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN2_PORTREG, CORE_PIN2_BIT), &CORE_PIN2_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN3_PORTREG, CORE_PIN3_BIT), &CORE_PIN3_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN4_PORTREG, CORE_PIN4_BIT), &CORE_PIN4_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN5_PORTREG, CORE_PIN5_BIT), &CORE_PIN5_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN6_PORTREG, CORE_PIN6_BIT), &CORE_PIN6_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN7_PORTREG, CORE_PIN7_BIT), &CORE_PIN7_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN8_PORTREG, CORE_PIN8_BIT), &CORE_PIN8_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN9_PORTREG, CORE_PIN9_BIT), &CORE_PIN9_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN10_PORTREG, CORE_PIN10_BIT), &CORE_PIN10_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN11_PORTREG, CORE_PIN11_BIT), &CORE_PIN11_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN12_PORTREG, CORE_PIN12_BIT), &CORE_PIN12_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN13_PORTREG, CORE_PIN13_BIT), &CORE_PIN13_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN14_PORTREG, CORE_PIN14_BIT), &CORE_PIN14_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN15_PORTREG, CORE_PIN15_BIT), &CORE_PIN15_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN16_PORTREG, CORE_PIN16_BIT), &CORE_PIN16_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN17_PORTREG, CORE_PIN17_BIT), &CORE_PIN17_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN18_PORTREG, CORE_PIN18_BIT), &CORE_PIN18_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN19_PORTREG, CORE_PIN19_BIT), &CORE_PIN19_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN20_PORTREG, CORE_PIN20_BIT), &CORE_PIN20_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN21_PORTREG, CORE_PIN21_BIT), &CORE_PIN21_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN22_PORTREG, CORE_PIN22_BIT), &CORE_PIN22_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN23_PORTREG, CORE_PIN23_BIT), &CORE_PIN23_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN24_PORTREG, CORE_PIN24_BIT), &CORE_PIN24_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN25_PORTREG, CORE_PIN25_BIT), &CORE_PIN25_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN26_PORTREG, CORE_PIN26_BIT), &CORE_PIN26_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN27_PORTREG, CORE_PIN27_BIT), &CORE_PIN27_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN28_PORTREG, CORE_PIN28_BIT), &CORE_PIN28_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN29_PORTREG, CORE_PIN29_BIT), &CORE_PIN29_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN30_PORTREG, CORE_PIN30_BIT), &CORE_PIN30_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN31_PORTREG, CORE_PIN31_BIT), &CORE_PIN31_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN32_PORTREG, CORE_PIN32_BIT), &CORE_PIN32_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN33_PORTREG, CORE_PIN33_BIT), &CORE_PIN33_CONFIG},
    #ifdef CORE_PIN34_PORTREG
    	{GPIO_BITBAND_PTR(CORE_PIN34_PORTREG, CORE_PIN34_BIT), &CORE_PIN34_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN35_PORTREG, CORE_PIN35_BIT), &CORE_PIN35_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN36_PORTREG, CORE_PIN36_BIT), &CORE_PIN36_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN37_PORTREG, CORE_PIN37_BIT), &CORE_PIN37_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN38_PORTREG, CORE_PIN38_BIT), &CORE_PIN38_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN39_PORTREG, CORE_PIN39_BIT), &CORE_PIN39_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN40_PORTREG, CORE_PIN40_BIT), &CORE_PIN40_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN41_PORTREG, CORE_PIN41_BIT), &CORE_PIN41_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN42_PORTREG, CORE_PIN42_BIT), &CORE_PIN42_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN43_PORTREG, CORE_PIN43_BIT), &CORE_PIN43_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN44_PORTREG, CORE_PIN44_BIT), &CORE_PIN44_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN45_PORTREG, CORE_PIN45_BIT), &CORE_PIN45_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN46_PORTREG, CORE_PIN46_BIT), &CORE_PIN46_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN47_PORTREG, CORE_PIN47_BIT), &CORE_PIN47_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN48_PORTREG, CORE_PIN48_BIT), &CORE_PIN48_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN49_PORTREG, CORE_PIN49_BIT), &CORE_PIN49_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN50_PORTREG, CORE_PIN50_BIT), &CORE_PIN50_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN51_PORTREG, CORE_PIN51_BIT), &CORE_PIN51_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN52_PORTREG, CORE_PIN52_BIT), &CORE_PIN52_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN53_PORTREG, CORE_PIN53_BIT), &CORE_PIN53_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN54_PORTREG, CORE_PIN54_BIT), &CORE_PIN54_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN55_PORTREG, CORE_PIN55_BIT), &CORE_PIN55_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN56_PORTREG, CORE_PIN56_BIT), &CORE_PIN56_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN57_PORTREG, CORE_PIN57_BIT), &CORE_PIN57_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN58_PORTREG, CORE_PIN58_BIT), &CORE_PIN58_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN59_PORTREG, CORE_PIN59_BIT), &CORE_PIN59_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN60_PORTREG, CORE_PIN60_BIT), &CORE_PIN60_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN61_PORTREG, CORE_PIN61_BIT), &CORE_PIN61_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN62_PORTREG, CORE_PIN62_BIT), &CORE_PIN62_CONFIG},
    	{GPIO_BITBAND_PTR(CORE_PIN63_PORTREG, CORE_PIN63_BIT), &CORE_PIN63_CONFIG},
    #ifdef TEENSY_3_6_PRO
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // filler entry for future use
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // filler entry for future use
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // filler entry for future use
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // filler entry for future use
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // filler entry for future use
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // filler entry for future use
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // filler entry for future use
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // filler entry for future use
    	{GPIO_BITBAND_PTR(CORE_PIN72_PORTREG, CORE_PIN72_BIT), &CORE_PIN72_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN73_PORTREG, CORE_PIN73_BIT), &CORE_PIN73_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN74_PORTREG, CORE_PIN74_BIT), &CORE_PIN74_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN75_PORTREG, CORE_PIN75_BIT), &CORE_PIN75_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN76_PORTREG, CORE_PIN76_BIT), &CORE_PIN76_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN77_PORTREG, CORE_PIN77_BIT), &CORE_PIN77_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN78_PORTREG, CORE_PIN78_BIT), &CORE_PIN78_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN79_PORTREG, CORE_PIN79_BIT), &CORE_PIN79_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN80_PORTREG, CORE_PIN80_BIT), &CORE_PIN80_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN81_PORTREG, CORE_PIN81_BIT), &CORE_PIN81_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN82_PORTREG, CORE_PIN82_BIT), &CORE_PIN82_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN83_PORTREG, CORE_PIN83_BIT), &CORE_PIN83_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN84_PORTREG, CORE_PIN84_BIT), &CORE_PIN84_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN85_PORTREG, CORE_PIN85_BIT), &CORE_PIN85_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN86_PORTREG, CORE_PIN86_BIT), &CORE_PIN86_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN87_PORTREG, CORE_PIN87_BIT), &CORE_PIN87_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN88_PORTREG, CORE_PIN88_BIT), &CORE_PIN88_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN89_PORTREG, CORE_PIN89_BIT), &CORE_PIN89_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN90_PORTREG, CORE_PIN90_BIT), &CORE_PIN90_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN91_PORTREG, CORE_PIN91_BIT), &CORE_PIN91_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN92_PORTREG, CORE_PIN92_BIT), &CORE_PIN92_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN93_PORTREG, CORE_PIN93_BIT), &CORE_PIN93_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN94_PORTREG, CORE_PIN94_BIT), &CORE_PIN94_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN95_PORTREG, CORE_PIN95_BIT), &CORE_PIN95_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN96_PORTREG, CORE_PIN96_BIT), &CORE_PIN96_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN97_PORTREG, CORE_PIN97_BIT), &CORE_PIN97_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN98_PORTREG, CORE_PIN98_BIT), &CORE_PIN98_CONFIG},  // new
    	{GPIO_BITBAND_PTR(CORE_PIN99_PORTREG, CORE_PIN99_BIT), &CORE_PIN99_CONFIG},  // new
    #endif
    #endif
    };
    
    #elif defined(KINETISL)
    const struct digital_pin_bitband_and_config_table_struct digital_pin_to_info_PGM[] = {
    	{((volatile uint8_t *)&CORE_PIN0_PORTREG + (CORE_PIN0_BIT >> 3)), &CORE_PIN0_CONFIG, (1<<(CORE_PIN0_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN1_PORTREG + (CORE_PIN1_BIT >> 3)), &CORE_PIN1_CONFIG, (1<<(CORE_PIN1_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN2_PORTREG + (CORE_PIN2_BIT >> 3)), &CORE_PIN2_CONFIG, (1<<(CORE_PIN2_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN3_PORTREG + (CORE_PIN3_BIT >> 3)), &CORE_PIN3_CONFIG, (1<<(CORE_PIN3_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN4_PORTREG + (CORE_PIN4_BIT >> 3)), &CORE_PIN4_CONFIG, (1<<(CORE_PIN4_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN5_PORTREG + (CORE_PIN5_BIT >> 3)), &CORE_PIN5_CONFIG, (1<<(CORE_PIN5_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN6_PORTREG + (CORE_PIN6_BIT >> 3)), &CORE_PIN6_CONFIG, (1<<(CORE_PIN6_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN7_PORTREG + (CORE_PIN7_BIT >> 3)), &CORE_PIN7_CONFIG, (1<<(CORE_PIN7_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN8_PORTREG + (CORE_PIN8_BIT >> 3)), &CORE_PIN8_CONFIG, (1<<(CORE_PIN8_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN9_PORTREG + (CORE_PIN9_BIT >> 3)), &CORE_PIN9_CONFIG, (1<<(CORE_PIN9_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN10_PORTREG + (CORE_PIN10_BIT >> 3)), &CORE_PIN10_CONFIG, (1<<(CORE_PIN10_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN11_PORTREG + (CORE_PIN11_BIT >> 3)), &CORE_PIN11_CONFIG, (1<<(CORE_PIN11_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN12_PORTREG + (CORE_PIN12_BIT >> 3)), &CORE_PIN12_CONFIG, (1<<(CORE_PIN12_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN13_PORTREG + (CORE_PIN13_BIT >> 3)), &CORE_PIN13_CONFIG, (1<<(CORE_PIN13_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN14_PORTREG + (CORE_PIN14_BIT >> 3)), &CORE_PIN14_CONFIG, (1<<(CORE_PIN14_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN15_PORTREG + (CORE_PIN15_BIT >> 3)), &CORE_PIN15_CONFIG, (1<<(CORE_PIN15_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN16_PORTREG + (CORE_PIN16_BIT >> 3)), &CORE_PIN16_CONFIG, (1<<(CORE_PIN16_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN17_PORTREG + (CORE_PIN17_BIT >> 3)), &CORE_PIN17_CONFIG, (1<<(CORE_PIN17_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN18_PORTREG + (CORE_PIN18_BIT >> 3)), &CORE_PIN18_CONFIG, (1<<(CORE_PIN18_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN19_PORTREG + (CORE_PIN19_BIT >> 3)), &CORE_PIN19_CONFIG, (1<<(CORE_PIN19_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN20_PORTREG + (CORE_PIN20_BIT >> 3)), &CORE_PIN20_CONFIG, (1<<(CORE_PIN20_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN21_PORTREG + (CORE_PIN21_BIT >> 3)), &CORE_PIN21_CONFIG, (1<<(CORE_PIN21_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN22_PORTREG + (CORE_PIN22_BIT >> 3)), &CORE_PIN22_CONFIG, (1<<(CORE_PIN22_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN23_PORTREG + (CORE_PIN23_BIT >> 3)), &CORE_PIN23_CONFIG, (1<<(CORE_PIN23_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN24_PORTREG + (CORE_PIN24_BIT >> 3)), &CORE_PIN24_CONFIG, (1<<(CORE_PIN24_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN25_PORTREG + (CORE_PIN25_BIT >> 3)), &CORE_PIN25_CONFIG, (1<<(CORE_PIN25_BIT & 7))},
    	{((volatile uint8_t *)&CORE_PIN26_PORTREG + (CORE_PIN26_BIT >> 3)), &CORE_PIN26_CONFIG, (1<<(CORE_PIN26_BIT & 7))}
    };
    
    #endif
    
    static void dummy_isr() {};
    
    typedef void (*voidFuncPtr)(void);
    #if defined(KINETISK)
    #ifdef NO_PORT_ISR_FASTRUN
    static void port_A_isr(void);
    static void port_B_isr(void);
    static void port_C_isr(void);
    static void port_D_isr(void);
    static void port_E_isr(void);
    #else
    static void port_A_isr(void) __attribute__ ((section(".fastrun"), noinline, noclone ));
    static void port_B_isr(void) __attribute__ ((section(".fastrun"), noinline, noclone ));
    static void port_C_isr(void) __attribute__ ((section(".fastrun"), noinline, noclone ));
    static void port_D_isr(void) __attribute__ ((section(".fastrun"), noinline, noclone ));
    static void port_E_isr(void) __attribute__ ((section(".fastrun"), noinline, noclone ));
    #endif
    
    voidFuncPtr isr_table_portA[CORE_MAX_PIN_PORTA+1] = { [0 ... CORE_MAX_PIN_PORTA] = dummy_isr };
    voidFuncPtr isr_table_portB[CORE_MAX_PIN_PORTB+1] = { [0 ... CORE_MAX_PIN_PORTB] = dummy_isr };
    voidFuncPtr isr_table_portC[CORE_MAX_PIN_PORTC+1] = { [0 ... CORE_MAX_PIN_PORTC] = dummy_isr };
    voidFuncPtr isr_table_portD[CORE_MAX_PIN_PORTD+1] = { [0 ... CORE_MAX_PIN_PORTD] = dummy_isr };
    voidFuncPtr isr_table_portE[CORE_MAX_PIN_PORTE+1] = { [0 ... CORE_MAX_PIN_PORTE] = dummy_isr };
    
    // The Pin Config Register is used to look up the correct interrupt table
    // for the corresponding port.
    static inline voidFuncPtr* getIsrTable(volatile uint32_t *config) {
    	voidFuncPtr* isr_table = NULL;
    	if(&PORTA_PCR0 <= config && config <= &PORTA_PCR31) isr_table = isr_table_portA;
    	else if(&PORTB_PCR0 <= config && config <= &PORTB_PCR31) isr_table = isr_table_portB;
    	else if(&PORTC_PCR0 <= config && config <= &PORTC_PCR31) isr_table = isr_table_portC;
    	else if(&PORTD_PCR0 <= config && config <= &PORTD_PCR31) isr_table = isr_table_portD;
    	else if(&PORTE_PCR0 <= config && config <= &PORTE_PCR31) isr_table = isr_table_portE;
    	return isr_table;
    }
    
    inline uint32_t getPinIndex(volatile uint32_t *config) {
    	uintptr_t v = (uintptr_t) config;
    	// There are 32 pin config registers for each port, each port starting at a round address.
    	// They are spaced 4 bytes apart.
    	return (v % 128) / 4;
    }
    #elif defined(KINETISL)
    volatile static voidFuncPtr intFunc[CORE_NUM_DIGITAL] = { [0 ... CORE_NUM_DIGITAL-1] = dummy_isr };
    static void porta_interrupt(void);
    static void portcd_interrupt(void);
    #endif
    
    void attachInterruptVector(enum IRQ_NUMBER_t irq, void (*function)(void))
    {
    	_VectorsRam[irq + 16] = function;
    }
    
    void attachInterrupt(uint8_t pin, void (*function)(void), int mode)
    {
    	volatile uint32_t *config;
    	uint32_t cfg, mask;
    
    	if (pin >= CORE_NUM_DIGITAL) return;
    	switch (mode) {
    	  case CHANGE:	mask = 0x0B; break;
    	  case RISING:	mask = 0x09; break;
    	  case FALLING:	mask = 0x0A; break;
    	  case LOW:	mask = 0x08; break;
    	  case HIGH:	mask = 0x0C; break;
    	  default: return;
    	}
    	mask = (mask << 16) | 0x01000000;
    	config = portConfigRegister(pin);
    	if ((*config & 0x00000700) == 0) {
    		// for compatibility with programs which depend
    		// on AVR hardware default to input mode.
    		pinMode(pin, INPUT);
    	}
    #if defined(KINETISK)
    	attachInterruptVector(IRQ_PORTA, port_A_isr);
    	attachInterruptVector(IRQ_PORTB, port_B_isr);
    	attachInterruptVector(IRQ_PORTC, port_C_isr);
    	attachInterruptVector(IRQ_PORTD, port_D_isr);
    	attachInterruptVector(IRQ_PORTE, port_E_isr);
    	voidFuncPtr* isr_table = getIsrTable(config);
    	if(!isr_table) return;
    	uint32_t pin_index = getPinIndex(config);
    	__disable_irq();
    	cfg = *config;
    	cfg &= ~0x000F0000;		// disable any previous interrupt
    	*config = cfg;
    	isr_table[pin_index] = function;	// set the function pointer
    	cfg |= mask;
    	*config = cfg;			// enable the new interrupt
    	__enable_irq();
    #elif defined(KINETISL)
    	attachInterruptVector(IRQ_PORTA, porta_interrupt);
    	attachInterruptVector(IRQ_PORTCD, portcd_interrupt);
    	__disable_irq();
    	cfg = *config;
    	cfg &= ~0x000F0000;		// disable any previous interrupt
    	*config = cfg;
    	intFunc[pin] = function;	// set the function pointer
    	cfg |= mask;
    	*config = cfg;			// enable the new interrupt
    	__enable_irq();
    #endif
    }
    
    void detachInterrupt(uint8_t pin)
    {
    	volatile uint32_t *config;
    
    	config = portConfigRegister(pin);
    #if defined(KINETISK)
    	voidFuncPtr* isr_table = getIsrTable(config);
    	if(!isr_table) return;
    	uint32_t pin_index = getPinIndex(config);
    	__disable_irq();
    	*config = ((*config & ~0x000F0000) | 0x01000000);
    	isr_table[pin_index] = dummy_isr;
    	__enable_irq();
    #elif defined(KINETISL)
    	__disable_irq();
    	*config = ((*config & ~0x000F0000) | 0x01000000);
    	intFunc[pin] = dummy_isr;
    	__enable_irq();
    #endif
    }
    
    
    typedef void (*voidFuncPtr)(void);
    
    // Using CTZ instead of CLZ is faster, since it allows more efficient bit
    // clearing and fast indexing into the pin ISR table.
    #define PORT_ISR_FUNCTION_CLZ(port_name) \
    	static void port_ ## port_name ## _isr(void) {            \
    		uint32_t isfr = PORT ## port_name ##_ISFR;            \
    		PORT ## port_name ##_ISFR = isfr;                     \
    		voidFuncPtr* isr_table = isr_table_port ## port_name; \
    		uint32_t bit_nr;                                      \
    		while(isfr) {                                         \
    			bit_nr = __builtin_ctz(isfr);                     \
    			isr_table[bit_nr]();                              \
    			isfr = isfr & (isfr-1);                           \
    			if(!isfr) return;                                 \
    		}                                                     \
    	}
    // END PORT_ISR_FUNCTION_CLZ
    
    #if defined(KINETISK)
    PORT_ISR_FUNCTION_CLZ(A)
    PORT_ISR_FUNCTION_CLZ(B)
    PORT_ISR_FUNCTION_CLZ(C)
    PORT_ISR_FUNCTION_CLZ(D)
    PORT_ISR_FUNCTION_CLZ(E)
    #elif defined(KINETISL)
    // Kinetis L (Teensy LC) is based on Cortex M0 and doesn't have hardware
    // support for CLZ.
    
    #define DISPATCH_PIN_ISR(pin_nr) { voidFuncPtr pin_isr = intFunc[pin_nr]; \
                                       if(isfr & CORE_PIN ## pin_nr ## _BITMASK) pin_isr(); }
    
    static void porta_interrupt(void)
    {
    	uint32_t isfr = PORTA_ISFR;
    	PORTA_ISFR = isfr;
    	DISPATCH_PIN_ISR(3);
    	DISPATCH_PIN_ISR(4);
    }
    
    static void portcd_interrupt(void)
    {
    	uint32_t isfr = PORTC_ISFR;
    	PORTC_ISFR = isfr;
    	DISPATCH_PIN_ISR(9);
    	DISPATCH_PIN_ISR(10);
    	DISPATCH_PIN_ISR(11);
    	DISPATCH_PIN_ISR(12);
    	DISPATCH_PIN_ISR(13);
    	DISPATCH_PIN_ISR(15);
    	DISPATCH_PIN_ISR(22);
    	DISPATCH_PIN_ISR(23);
    	isfr = PORTD_ISFR;
    	PORTD_ISFR = isfr;
    	DISPATCH_PIN_ISR(2);
    	DISPATCH_PIN_ISR(5);
    	DISPATCH_PIN_ISR(6);
    	DISPATCH_PIN_ISR(7);
    	DISPATCH_PIN_ISR(8);
    	DISPATCH_PIN_ISR(14);
    	DISPATCH_PIN_ISR(20);
    	DISPATCH_PIN_ISR(21);
    }
    #undef DISPATCH_PIN_ISR
    
    #endif
    
    
    #if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
    
    unsigned long rtc_get(void)
    {
    	return RTC_TSR;
    }
    
    void rtc_set(unsigned long t)
    {
    	RTC_SR = 0;
    	RTC_TPR = 0;
    	RTC_TSR = t;
    	RTC_SR = RTC_SR_TCE;
    }
    
    // adjust is the amount of crystal error to compensate, 1 = 0.1192 ppm
    // For example, adjust = -100 is slows the clock by 11.92 ppm
    //
    void rtc_compensate(int adjust)
    {
    	uint32_t comp, interval, tcr;
    
    	// This simple approach tries to maximize the interval.
    	// Perhaps minimizing TCR would be better, so the
    	// compensation is distributed more evenly across
    	// many seconds, rather than saving it all up and then
    	// altering one second up to +/- 0.38%
    	if (adjust >= 0) {
    		comp = adjust;
    		interval = 256;
    		while (1) {
    			tcr = comp * interval;
    			if (tcr < 128*256) break;
    			if (--interval == 1) break;
    		}
    		tcr = tcr >> 8;
    	} else {
    		comp = -adjust;
    		interval = 256;
    		while (1) {
    			tcr = comp * interval;
    			if (tcr < 129*256) break;
    			if (--interval == 1) break;
    		}
    		tcr = tcr >> 8;
    		tcr = 256 - tcr;
    	}
    	RTC_TCR = ((interval - 1) << 8) | tcr;
    }
    
    #else
    
    unsigned long rtc_get(void) { return 0; }
    void rtc_set(unsigned long t) { }
    void rtc_compensate(int adjust) { }
    
    #endif
    
    
    
    #if 0
    // TODO: build system should define this
    // so RTC is automatically initialized to approx correct time
    // at least when the program begins running right after upload
    #ifndef TIME_T
    #define TIME_T 1350160272
    #endif
    
    void init_rtc(void)
    {
    	serial_print("init_rtc\n");
    	//SIM_SCGC6 |= SIM_SCGC6_RTC;
    
    	// enable the RTC crystal oscillator, for approx 12pf crystal
    	if (!(RTC_CR & RTC_CR_OSCE)) {
    		serial_print("start RTC oscillator\n");
    		RTC_SR = 0;
    		RTC_CR = RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE;
    	}
    	// should wait for crystal to stabilize.....
    
    	serial_print("SR=");
    	serial_phex32(RTC_SR);
    	serial_print("\n");
    	serial_print("CR=");
    	serial_phex32(RTC_CR);
    	serial_print("\n");
    	serial_print("TSR=");
    	serial_phex32(RTC_TSR);
    	serial_print("\n");
    	serial_print("TCR=");
    	serial_phex32(RTC_TCR);
    	serial_print("\n");
    
    	if (RTC_SR & RTC_SR_TIF) {
    		// enable the RTC
    		RTC_SR = 0;
    		RTC_TPR = 0;
    		RTC_TSR = TIME_T;
    		RTC_SR = RTC_SR_TCE;
    	}
    }
    #endif
    
    extern void usb_init(void);
    
    
    // create a default PWM at the same 488.28 Hz as Arduino Uno
    
    #if defined(KINETISK)
    #define F_TIMER F_BUS
    #elif defined(KINETISL)
    
    #if F_CPU > 16000000
    #define F_TIMER (F_PLL/2)
    #else 
    #define F_TIMER (F_PLL)
    #endif//Low Power
    
    #endif
    
    #if F_TIMER == 120000000
    #define DEFAULT_FTM_MOD (61440 - 1)
    #define DEFAULT_FTM_PRESCALE 2
    #elif F_TIMER == 108000000
    #define DEFAULT_FTM_MOD (55296 - 1)
    #define DEFAULT_FTM_PRESCALE 2
    #elif F_TIMER == 96000000
    #define DEFAULT_FTM_MOD (49152 - 1)
    #define DEFAULT_FTM_PRESCALE 2
    #elif F_TIMER == 90000000
    #define DEFAULT_FTM_MOD (46080 - 1)
    #define DEFAULT_FTM_PRESCALE 2
    #elif F_TIMER == 80000000
    #define DEFAULT_FTM_MOD (40960 - 1)
    #define DEFAULT_FTM_PRESCALE 2
    #elif F_TIMER == 72000000
    #define DEFAULT_FTM_MOD (36864 - 1)
    #define DEFAULT_FTM_PRESCALE 2
    #elif F_TIMER == 64000000
    #define DEFAULT_FTM_MOD (65536 - 1)
    #define DEFAULT_FTM_PRESCALE 1
    #elif F_TIMER == 60000000
    #define DEFAULT_FTM_MOD (61440 - 1)
    #define DEFAULT_FTM_PRESCALE 1
    #elif F_TIMER == 56000000
    #define DEFAULT_FTM_MOD (57344 - 1)
    #define DEFAULT_FTM_PRESCALE 1
    #elif F_TIMER == 54000000
    #define DEFAULT_FTM_MOD (55296 - 1)
    #define DEFAULT_FTM_PRESCALE 1
    #elif F_TIMER == 48000000
    #define DEFAULT_FTM_MOD (49152 - 1)
    #define DEFAULT_FTM_PRESCALE 1
    #elif F_TIMER == 40000000
    #define DEFAULT_FTM_MOD (40960 - 1)
    #define DEFAULT_FTM_PRESCALE 1
    #elif F_TIMER == 36000000
    #define DEFAULT_FTM_MOD (36864 - 1)
    #define DEFAULT_FTM_PRESCALE 1
    #elif F_TIMER == 24000000
    #define DEFAULT_FTM_MOD (49152 - 1)
    #define DEFAULT_FTM_PRESCALE 0
    #elif F_TIMER == 16000000
    #define DEFAULT_FTM_MOD (32768 - 1)
    #define DEFAULT_FTM_PRESCALE 0
    #elif F_TIMER == 8000000
    #define DEFAULT_FTM_MOD (16384 - 1)
    #define DEFAULT_FTM_PRESCALE 0
    #elif F_TIMER == 4000000
    #define DEFAULT_FTM_MOD (8192 - 1)
    #define DEFAULT_FTM_PRESCALE 0
    #elif F_TIMER == 2000000
    #define DEFAULT_FTM_MOD (4096 - 1)
    #define DEFAULT_FTM_PRESCALE 0
    #endif
    
    //void init_pins(void)
    __attribute__((noinline))
    void _init_Teensyduino_internal_(void)
    {
    #if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
    	NVIC_ENABLE_IRQ(IRQ_PORTA);
    	NVIC_ENABLE_IRQ(IRQ_PORTB);
    	NVIC_ENABLE_IRQ(IRQ_PORTC);
    	NVIC_ENABLE_IRQ(IRQ_PORTD);
    	NVIC_ENABLE_IRQ(IRQ_PORTE);
    #elif defined(__MKL26Z64__)
    	NVIC_ENABLE_IRQ(IRQ_PORTA);
    	NVIC_ENABLE_IRQ(IRQ_PORTCD);
    #endif
    	//SIM_SCGC6 |= SIM_SCGC6_FTM0;	// TODO: use bitband for atomic read-mod-write
    	//SIM_SCGC6 |= SIM_SCGC6_FTM1;
    	FTM0_CNT = 0;
    	FTM0_MOD = DEFAULT_FTM_MOD;
    	FTM0_C0SC = 0x28; // MSnB:MSnA = 10, ELSnB:ELSnA = 10
    	FTM0_C1SC = 0x28;
    	FTM0_C2SC = 0x28;
    	FTM0_C3SC = 0x28;
    	FTM0_C4SC = 0x28;
    	FTM0_C5SC = 0x28;
    #if defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__)
    	FTM0_C6SC = 0x28;
    	FTM0_C7SC = 0x28;
    #endif
    #if defined(__MK64FX512__) || defined(__MK66FX1M0__)
    	FTM3_C0SC = 0x28;
    	FTM3_C1SC = 0x28;
    	FTM3_C2SC = 0x28;
    	FTM3_C3SC = 0x28;
    	FTM3_C4SC = 0x28;
    	FTM3_C5SC = 0x28;
    	FTM3_C6SC = 0x28;
    	FTM3_C7SC = 0x28;
    #endif
    	FTM0_SC = FTM_SC_CLKS(1) | FTM_SC_PS(DEFAULT_FTM_PRESCALE);
    	FTM1_CNT = 0;
    	FTM1_MOD = DEFAULT_FTM_MOD;
    	FTM1_C0SC = 0x28;
    	FTM1_C1SC = 0x28;
    	FTM1_SC = FTM_SC_CLKS(1) | FTM_SC_PS(DEFAULT_FTM_PRESCALE);
    #if defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__) || defined(__MKL26Z64__)
    	FTM2_CNT = 0;
    	FTM2_MOD = DEFAULT_FTM_MOD;
    	FTM2_C0SC = 0x28;
    	FTM2_C1SC = 0x28;
    	FTM2_SC = FTM_SC_CLKS(1) | FTM_SC_PS(DEFAULT_FTM_PRESCALE);
    #endif
    #if defined(__MK64FX512__) || defined(__MK66FX1M0__)
    	FTM3_CNT = 0;
    	FTM3_MOD = DEFAULT_FTM_MOD;
    	FTM3_C0SC = 0x28;
    	FTM3_C1SC = 0x28;
    	FTM3_SC = FTM_SC_CLKS(1) | FTM_SC_PS(DEFAULT_FTM_PRESCALE);
    #endif
    #if defined(__MK66FX1M0__)
    	SIM_SCGC2 |= SIM_SCGC2_TPM1;
    	SIM_SOPT2 |= SIM_SOPT2_TPMSRC(2);
    	TPM1_CNT = 0;
    	TPM1_MOD = 32767;
    	TPM1_C0SC = 0x28;
    	TPM1_C1SC = 0x28;
    	TPM1_SC = FTM_SC_CLKS(1) | FTM_SC_PS(0);
    #endif
    	analog_init();
    	// for background about this startup delay, please see these conversations
    	// https://forum.pjrc.com/threads/36606-startup-time-(400ms)?p=113980&viewfull=1#post113980
    	// https://forum.pjrc.com/threads/31290-Teensey-3-2-Teensey-Loader-1-24-Issues?p=87273&viewfull=1#post87273
    #if TEENSYDUINO >= 142
    	delay(25);
    	usb_init();
    	delay(275);
    #else
    	delay(50);
    	usb_init();
    	delay(350);
    #endif
    }
    
    
    #if defined(__MK20DX128__)
    #define FTM0_CH0_PIN 22
    #define FTM0_CH1_PIN 23
    #define FTM0_CH2_PIN  9
    #define FTM0_CH3_PIN 10
    #define FTM0_CH4_PIN  6
    #define FTM0_CH5_PIN 20
    #define FTM0_CH6_PIN 21
    #define FTM0_CH7_PIN  5
    #define FTM1_CH0_PIN  3
    #define FTM1_CH1_PIN  4
    #elif defined(__MK20DX256__)
    #define FTM0_CH0_PIN 22
    #define FTM0_CH1_PIN 23
    #define FTM0_CH2_PIN  9
    #define FTM0_CH3_PIN 10
    #define FTM0_CH4_PIN  6
    #define FTM0_CH5_PIN 20
    #define FTM0_CH6_PIN 21
    #define FTM0_CH7_PIN  5
    #define FTM1_CH0_PIN  3
    #define FTM1_CH1_PIN  4
    #define FTM2_CH0_PIN 32
    #define FTM2_CH1_PIN 25
    #elif defined(__MKL26Z64__)
    #define FTM0_CH0_PIN 22
    #define FTM0_CH1_PIN 23
    #define FTM0_CH2_PIN  9
    #define FTM0_CH3_PIN 10
    #define FTM0_CH4_PIN  6
    #define FTM0_CH5_PIN 20
    #define FTM1_CH0_PIN 16
    #define FTM1_CH1_PIN 17
    #define FTM2_CH0_PIN  3
    #define FTM2_CH1_PIN  4
    #elif defined(__MK64FX512__)
    #define FTM0_CH0_PIN 22
    #define FTM0_CH1_PIN 23
    #define FTM0_CH2_PIN  9
    #define FTM0_CH3_PIN 10
    #define FTM0_CH4_PIN  6
    #define FTM0_CH5_PIN 20
    #define FTM0_CH6_PIN 21
    #define FTM0_CH7_PIN  5
    #define FTM1_CH0_PIN  3
    #define FTM1_CH1_PIN  4
    #define FTM2_CH0_PIN 29
    #define FTM2_CH1_PIN 30
    #define FTM3_CH0_PIN  2
    #define FTM3_CH1_PIN 14
    #define FTM3_CH2_PIN  7
    #define FTM3_CH3_PIN  8
    #define FTM3_CH4_PIN 35
    #define FTM3_CH5_PIN 36
    #define FTM3_CH6_PIN 37
    #define FTM3_CH7_PIN 38
    #elif defined(__MK66FX1M0__)
    #define FTM0_CH0_PIN 22
    #define FTM0_CH1_PIN 23
    #define FTM0_CH2_PIN  9
    #define FTM0_CH3_PIN 10
    #define FTM0_CH4_PIN  6
    #define FTM0_CH5_PIN 20
    #define FTM0_CH6_PIN 21
    #define FTM0_CH7_PIN  5
    #define FTM1_CH0_PIN  3
    #define FTM1_CH1_PIN  4
    #define FTM2_CH0_PIN 29
    #define FTM2_CH1_PIN 30
    #define FTM3_CH0_PIN  2
    #define FTM3_CH1_PIN 14
    #define FTM3_CH2_PIN  7
    #define FTM3_CH3_PIN  8
    #define FTM3_CH4_PIN 35
    #define FTM3_CH5_PIN 36
    #define FTM3_CH6_PIN 37
    #define FTM3_CH7_PIN 38
    #define TPM1_CH0_PIN 16
    #define TPM1_CH1_PIN 17
    #endif
    #define FTM_PINCFG(pin) FTM_PINCFG2(pin)
    #define FTM_PINCFG2(pin) CORE_PIN ## pin ## _CONFIG
    
    static uint8_t analog_write_res = 8;
    
    // SOPT4 is SIM select clocks?
    // FTM is clocked by the bus clock, either 24 or 48 MHz
    // input capture can be FTM1_CH0, CMP0 or CMP1 or USB start of frame
    // 24 MHz with reload 49152 to match Arduino's speed = 488.28125 Hz
    
    void analogWrite(uint8_t pin, int val)
    {
    	uint32_t cval, max;
    
    #if defined(__MK20DX256__)
    	if (pin == A14) {
    		uint8_t res = analog_write_res;
    		if (res < 12) {
    			val <<= 12 - res;
    		} else if (res > 12) {
    			val >>= res - 12;
    		}
    		analogWriteDAC0(val);
    		return;
    	}
    #elif defined(__MKL26Z64__)
    	if (pin == A12) {
    		uint8_t res = analog_write_res;
    		if (res < 12) {
    			val <<= 12 - res;
    		} else if (res > 12) {
    			val >>= res - 12;
    		}
    		analogWriteDAC0(val);
    		return;
    	}
    #elif defined(__MK64FX512__) || defined(__MK66FX1M0__)
    	if (pin == A21 || pin == A22) {
    		uint8_t res = analog_write_res;
    		if (res < 12) {
    			val <<= 12 - res;
    		} else if (res > 12) {
    			val >>= res - 12;
    		}
    		if (pin == A21) analogWriteDAC0(val);
    		else analogWriteDAC1(val);
    		return;
    	}
    #endif
    
    	max = 1 << analog_write_res;
    	if (val <= 0) {
    		digitalWrite(pin, LOW);
    		pinMode(pin, OUTPUT);	// TODO: implement OUTPUT_LOW
    		return;
    	} else if (val >= max) {
    		digitalWrite(pin, HIGH);
    		pinMode(pin, OUTPUT);	// TODO: implement OUTPUT_HIGH
    		return;
    	}
    
    	//serial_print("analogWrite\n");
    	//serial_print("val = ");
    	//serial_phex32(val);
    	//serial_print("\n");
    	//serial_print("analog_write_res = ");
    	//serial_phex(analog_write_res);
    	//serial_print("\n");
    	if (pin == FTM1_CH0_PIN || pin == FTM1_CH1_PIN) {
    		cval = ((uint32_t)val * (uint32_t)(FTM1_MOD + 1)) >> analog_write_res;
    #if defined(FTM2_CH0_PIN)
    	} else if (pin == FTM2_CH0_PIN || pin == FTM2_CH1_PIN) {
    		cval = ((uint32_t)val * (uint32_t)(FTM2_MOD + 1)) >> analog_write_res;
    #endif
    #if defined(FTM3_CH0_PIN)
    	} else if (pin == FTM3_CH0_PIN || pin == FTM3_CH1_PIN || pin == FTM3_CH2_PIN
    	  || pin == FTM3_CH3_PIN || pin == FTM3_CH4_PIN || pin == FTM3_CH5_PIN
    	  || pin == FTM3_CH6_PIN || pin == FTM3_CH7_PIN) {
    		cval = ((uint32_t)val * (uint32_t)(FTM3_MOD + 1)) >> analog_write_res;
    #endif
    #if defined(TPM1_CH0_PIN)
    	} else if (pin == TPM1_CH0_PIN || pin == TPM1_CH1_PIN) {
    		cval = ((uint32_t)val * (uint32_t)(TPM1_MOD + 1)) >> analog_write_res;
    #endif
    	} else {
    		cval = ((uint32_t)val * (uint32_t)(FTM0_MOD + 1)) >> analog_write_res;
    	}
    	//serial_print("cval = ");
    	//serial_phex32(cval);
    	//serial_print("\n");
    	switch (pin) {
    #ifdef FTM0_CH0_PIN
    	  case FTM0_CH0_PIN: // PTC1, FTM0_CH0
    		FTM0_C0V = cval;
    		FTM_PINCFG(FTM0_CH0_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM0_CH1_PIN
    	  case FTM0_CH1_PIN: // PTC2, FTM0_CH1
    		FTM0_C1V = cval;
    		FTM_PINCFG(FTM0_CH1_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM0_CH2_PIN
    	  case FTM0_CH2_PIN: // PTC3, FTM0_CH2
    		FTM0_C2V = cval;
    		FTM_PINCFG(FTM0_CH2_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM0_CH3_PIN
    	  case FTM0_CH3_PIN: // PTC4, FTM0_CH3
    		FTM0_C3V = cval;
    		FTM_PINCFG(FTM0_CH3_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM0_CH4_PIN
    	  case FTM0_CH4_PIN: // PTD4, FTM0_CH4
    		FTM0_C4V = cval;
    		FTM_PINCFG(FTM0_CH4_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM0_CH5_PIN
    	  case FTM0_CH5_PIN: // PTD5, FTM0_CH5
    		FTM0_C5V = cval;
    		FTM_PINCFG(FTM0_CH5_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM0_CH6_PIN
    	  case FTM0_CH6_PIN: // PTD6, FTM0_CH6
    		FTM0_C6V = cval;
    		FTM_PINCFG(FTM0_CH6_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM0_CH7_PIN
    	  case FTM0_CH7_PIN: // PTD7, FTM0_CH7
    		FTM0_C7V = cval;
    		FTM_PINCFG(FTM0_CH7_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM1_CH0_PIN
    	  case FTM1_CH0_PIN: // PTA12, FTM1_CH0
    		FTM1_C0V = cval;
    		FTM_PINCFG(FTM1_CH0_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM1_CH1_PIN
    	  case FTM1_CH1_PIN: // PTA13, FTM1_CH1
    		FTM1_C1V = cval;
    		FTM_PINCFG(FTM1_CH1_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM2_CH0_PIN
    	  case FTM2_CH0_PIN: // PTB18, FTM2_CH0
    		FTM2_C0V = cval;
    		FTM_PINCFG(FTM2_CH0_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM2_CH1_PIN
    	  case FTM2_CH1_PIN: // PTB19, FTM1_CH1
    		FTM2_C1V = cval;
    		FTM_PINCFG(FTM2_CH1_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM3_CH0_PIN
    	  case FTM3_CH0_PIN:
    		FTM3_C0V = cval;
    		FTM_PINCFG(FTM3_CH0_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM3_CH1_PIN
    	  case FTM3_CH1_PIN:
    		FTM3_C1V = cval;
    		FTM_PINCFG(FTM3_CH1_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM3_CH2_PIN
    	  case FTM3_CH2_PIN:
    		FTM3_C2V = cval;
    		FTM_PINCFG(FTM3_CH2_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM3_CH3_PIN
    	  case FTM3_CH3_PIN:
    		FTM3_C3V = cval;
    		FTM_PINCFG(FTM3_CH3_PIN) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM3_CH4_PIN
    	  case FTM3_CH4_PIN:
    		FTM3_C4V = cval;
    		FTM_PINCFG(FTM3_CH4_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM3_CH5_PIN
    	  case FTM3_CH5_PIN:
    		FTM3_C5V = cval;
    		FTM_PINCFG(FTM3_CH5_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM3_CH6_PIN
    	  case FTM3_CH6_PIN:
    		FTM3_C6V = cval;
    		FTM_PINCFG(FTM3_CH6_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef FTM3_CH7_PIN
    	  case FTM3_CH7_PIN:
    		FTM3_C7V = cval;
    		FTM_PINCFG(FTM3_CH7_PIN) = PORT_PCR_MUX(3) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef TPM1_CH0_PIN
    	  case TPM1_CH0_PIN:
    		TPM1_C0V = cval;
    		FTM_PINCFG(TPM1_CH0_PIN) = PORT_PCR_MUX(6) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    #ifdef TPM1_CH1_PIN
    	  case TPM1_CH1_PIN:
    		TPM1_C1V = cval;
    		FTM_PINCFG(TPM1_CH1_PIN) = PORT_PCR_MUX(6) | PORT_PCR_DSE | PORT_PCR_SRE;
    		break;
    #endif
    	  default:
    		digitalWrite(pin, (val > 127) ? HIGH : LOW);
    		pinMode(pin, OUTPUT);
    	}
    }
    
    
    uint32_t analogWriteRes(uint32_t bits)
    {
    	uint32_t prior_res;
    	if (bits < 1) {
    		bits = 1;
    	} else if (bits > 16) {
    		bits = 16;
    	}
    	prior_res = analog_write_res;
    	analog_write_res = bits;
    	return prior_res;
    }
    
    
    void analogWriteFrequency(uint8_t pin, float frequency)
    {
    	uint32_t prescale, mod, ftmClock, ftmClockSource;
    	float minfreq;
    
    	//serial_print("analogWriteFrequency: pin = ");
    	//serial_phex(pin);
    	//serial_print(", freq = ");
    	//serial_phex32((uint32_t)frequency);
    	//serial_print("\n");
    
    #ifdef TPM1_CH0_PIN
    	if (pin == TPM1_CH0_PIN || pin == TPM1_CH1_PIN) {
    		ftmClockSource = 1;
    		ftmClock = 16000000;
    	} else
    #endif
    #if defined(__MKL26Z64__)
    	// Teensy LC does not support slow clock source (ftmClockSource = 2)
    	ftmClockSource = 1; 	// Use default F_TIMER clock source
    	ftmClock = F_TIMER;	// Set variable for the actual timer clock frequency
    #else
    	if (frequency < (float)(F_TIMER >> 7) / 65536.0f) {
    		// frequency is too low for working with F_TIMER:
    		ftmClockSource = 2; 	// Use alternative 31250Hz clock source
    		ftmClock = 31250;   	// Set variable for the actual timer clock frequency
    	} else {
    		ftmClockSource = 1; 	// Use default F_TIMER clock source
    		ftmClock = F_TIMER;	// Set variable for the actual timer clock frequency
    	}
    #endif
    
    	
    	for (prescale = 0; prescale < 7; prescale++) {
    		minfreq = (float)(ftmClock >> prescale) / 65536.0f;	//Use ftmClock instead of F_TIMER
    		if (frequency >= minfreq) break;
    	}
    	//serial_print("F_TIMER/ftm_Clock = ");
    	//serial_phex32(ftmClock >> prescale);
    	//serial_print("\n");
    	//serial_print("prescale = ");
    	//serial_phex(prescale);
    	//serial_print("\n");
    	mod = (float)(ftmClock >> prescale) / frequency - 0.5f;	//Use ftmClock instead of F_TIMER
    	if (mod > 65535) mod = 65535;
    	//serial_print("mod = ");
    	//serial_phex32(mod);
    	//serial_print("\n");
    	if (pin == FTM1_CH0_PIN || pin == FTM1_CH1_PIN) {
    		FTM1_SC = 0;
    		FTM1_CNT = 0;
    		FTM1_MOD = mod;
    		FTM1_SC = FTM_SC_CLKS(ftmClockSource) | FTM_SC_PS(prescale);	//Use ftmClockSource instead of 1
    	} else if (pin == FTM0_CH0_PIN || pin == FTM0_CH1_PIN
    	  || pin == FTM0_CH2_PIN || pin == FTM0_CH3_PIN
    	  || pin == FTM0_CH4_PIN || pin == FTM0_CH5_PIN
    #ifdef FTM0_CH6_PIN
    	  || pin == FTM0_CH6_PIN || pin == FTM0_CH7_PIN
    #endif
    	  ) {
    		FTM0_SC = 0;
    		FTM0_CNT = 0;
    		FTM0_MOD = mod;
    		FTM0_SC = FTM_SC_CLKS(ftmClockSource) | FTM_SC_PS(prescale);	//Use ftmClockSource instead of 1
    	}
    #ifdef FTM2_CH0_PIN
    	  else if (pin == FTM2_CH0_PIN || pin == FTM2_CH1_PIN) {
    		FTM2_SC = 0;
    		FTM2_CNT = 0;
    		FTM2_MOD = mod;
    		FTM2_SC = FTM_SC_CLKS(ftmClockSource) | FTM_SC_PS(prescale);	//Use ftmClockSource instead of 1
    	}
    #endif
    #ifdef FTM3_CH0_PIN
    	  else if (pin == FTM3_CH0_PIN || pin == FTM3_CH1_PIN
    	  || pin == FTM3_CH2_PIN || pin == FTM3_CH3_PIN
    	  || pin == FTM3_CH4_PIN || pin == FTM3_CH5_PIN
    	  || pin == FTM3_CH6_PIN || pin == FTM3_CH7_PIN) {
    		FTM3_SC = 0;
    		FTM3_CNT = 0;
    		FTM3_MOD = mod;
    		FTM3_SC = FTM_SC_CLKS(ftmClockSource) | FTM_SC_PS(prescale);	//Use the new ftmClockSource instead of 1
    	}
    #endif
    #ifdef TPM1_CH0_PIN
    	  else if (pin == TPM1_CH0_PIN || pin == TPM1_CH1_PIN) {
    		TPM1_SC = 0;
    		TPM1_CNT = 0;
    		TPM1_MOD = mod;
    		TPM1_SC = FTM_SC_CLKS(ftmClockSource) | FTM_SC_PS(prescale);
    	}
    #endif
    }
    
    
    
    // TODO: startup code needs to initialize all pins to GPIO mode, input by default
    
    void digitalWrite(uint8_t pin, uint8_t val)
    {
    	if (pin >= CORE_NUM_DIGITAL) return;
    #ifdef KINETISK
    	if (*portModeRegister(pin)) {
    		if (val) {
    			*portSetRegister(pin) = 1;
    		} else {
    			*portClearRegister(pin) = 1;
    		}
    #else
    	if (*portModeRegister(pin) & digitalPinToBitMask(pin)) {
    		if (val) {
    			*portSetRegister(pin) = digitalPinToBitMask(pin);
    		} else {
    			*portClearRegister(pin) = digitalPinToBitMask(pin);
    		}
    #endif
    	} else {
    		volatile uint32_t *config = portConfigRegister(pin);
    		if (val) {
    			// TODO use bitband for atomic read-mod-write
    			*config |= (PORT_PCR_PE | PORT_PCR_PS);
    			//*config = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS;
    		} else {
    			// TODO use bitband for atomic read-mod-write
    			*config &= ~(PORT_PCR_PE);
    			//*config = PORT_PCR_MUX(1);
    		}
    	}
    
    }
    
    uint8_t digitalRead(uint8_t pin)
    {
    	if (pin >= CORE_NUM_DIGITAL) return 0;
    #ifdef KINETISK
    	return *portInputRegister(pin);
    #else
    	return (*portInputRegister(pin) & digitalPinToBitMask(pin)) ? 1 : 0;
    #endif
    }
    
    
    
    void pinMode(uint8_t pin, uint8_t mode)
    {
    	volatile uint32_t *config;
    
    	if (pin >= CORE_NUM_DIGITAL) return;
    	config = portConfigRegister(pin);
    
    	if (mode == OUTPUT || mode == OUTPUT_OPENDRAIN) {
    #ifdef KINETISK
    		*portModeRegister(pin) = 1;
    #else
    		*portModeRegister(pin) |= digitalPinToBitMask(pin); // TODO: atomic
    #endif
    		*config = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
    		if (mode == OUTPUT_OPENDRAIN) {
    		    *config |= PORT_PCR_ODE;
    		} else {
    		    *config &= ~PORT_PCR_ODE;
                    }
    	} else {
    #ifdef KINETISK
    		*portModeRegister(pin) = 0;
    #else
    		*portModeRegister(pin) &= ~digitalPinToBitMask(pin);
    #endif
    		if (mode == INPUT) {
    			*config = PORT_PCR_MUX(1);
    		} else if (mode == INPUT_PULLUP) {
    			*config = PORT_PCR_MUX(1) | PORT_PCR_PE | PORT_PCR_PS;
    		} else if (mode == INPUT_PULLDOWN) {
    			*config = PORT_PCR_MUX(1) | PORT_PCR_PE;
    		} else { // INPUT_DISABLE
    			*config = 0;
    		}
    	}
    }
    
    
    void _shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t value)
    {
            if (bitOrder == LSBFIRST) {
                    shiftOut_lsbFirst(dataPin, clockPin, value);
            } else {
                    shiftOut_msbFirst(dataPin, clockPin, value);
            }
    }
    
    void shiftOut_lsbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value)
    {
            uint8_t mask;
            for (mask=0x01; mask; mask <<= 1) {
                    digitalWrite(dataPin, value & mask);
                    digitalWrite(clockPin, HIGH);
                    digitalWrite(clockPin, LOW);
            }
    }
    
    void shiftOut_msbFirst(uint8_t dataPin, uint8_t clockPin, uint8_t value)
    {
            uint8_t mask;
            for (mask=0x80; mask; mask >>= 1) {
                    digitalWrite(dataPin, value & mask);
                    digitalWrite(clockPin, HIGH);
                    digitalWrite(clockPin, LOW);
            }
    }
    
    uint8_t _shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder)
    {
            if (bitOrder == LSBFIRST) {
                    return shiftIn_lsbFirst(dataPin, clockPin);
            } else {
                    return shiftIn_msbFirst(dataPin, clockPin);
            }
    }
    
    uint8_t shiftIn_lsbFirst(uint8_t dataPin, uint8_t clockPin)
    {
            uint8_t mask, value=0;
            for (mask=0x01; mask; mask <<= 1) {
                    digitalWrite(clockPin, HIGH);
                    if (digitalRead(dataPin)) value |= mask;
                    digitalWrite(clockPin, LOW);
            }
            return value;
    }
    
    uint8_t shiftIn_msbFirst(uint8_t dataPin, uint8_t clockPin)
    {
            uint8_t mask, value=0;
            for (mask=0x80; mask; mask >>= 1) {
                    digitalWrite(clockPin, HIGH);
                    if (digitalRead(dataPin)) value |= mask;
                    digitalWrite(clockPin, LOW);
            }
            return value;
    }
    
    
    
    // the systick interrupt is supposed to increment this at 1 kHz rate
    volatile uint32_t systick_millis_count = 0;
    
    //uint32_t systick_current, systick_count, systick_istatus;  // testing only
    
    uint32_t micros(void)
    {
    	uint32_t count, current, istatus;
    
    	__disable_irq();
    	current = SYST_CVR;
    	count = systick_millis_count;
    	istatus = SCB_ICSR;	// bit 26 indicates if systick exception pending
    	__enable_irq();
    	 //systick_current = current;
    	 //systick_count = count;
    	 //systick_istatus = istatus & SCB_ICSR_PENDSTSET ? 1 : 0;
    	if ((istatus & SCB_ICSR_PENDSTSET) && current > 50) count++;
    	current = ((F_CPU / 1000) - 1) - current;
    #if defined(KINETISL) && F_CPU == 48000000
    	return count * 1000 + ((current * (uint32_t)87381) >> 22);
    #elif defined(KINETISL) && F_CPU == 24000000
    	return count * 1000 + ((current * (uint32_t)174763) >> 22);
    #endif
    	return count * 1000 + current / (F_CPU / 1000000);
    }
    
    void delay(uint32_t ms)
    {
    	uint32_t start = micros();
    
    	if (ms > 0) {
    		while (1) {
    			while ((micros() - start) >= 1000) {
    				ms--;
    				if (ms == 0) return;
    				start += 1000;
    			}
    			yield();
    		}
    	}
    }
    
    // TODO: verify these result in correct timeouts...
    #if F_CPU == 240000000
    #define PULSEIN_LOOPS_PER_USEC 33
    #elif F_CPU == 216000000
    #define PULSEIN_LOOPS_PER_USEC 31
    #elif F_CPU == 192000000
    #define PULSEIN_LOOPS_PER_USEC 29
    #elif F_CPU == 180000000
    #define PULSEIN_LOOPS_PER_USEC 27
    #elif F_CPU == 168000000
    #define PULSEIN_LOOPS_PER_USEC 25
    #elif F_CPU == 144000000
    #define PULSEIN_LOOPS_PER_USEC 21
    #elif F_CPU == 120000000
    #define PULSEIN_LOOPS_PER_USEC 18
    #elif F_CPU == 96000000
    #define PULSEIN_LOOPS_PER_USEC 14
    #elif F_CPU == 72000000
    #define PULSEIN_LOOPS_PER_USEC 10
    #elif F_CPU == 48000000
    #define PULSEIN_LOOPS_PER_USEC 7
    #elif F_CPU == 24000000
    #define PULSEIN_LOOPS_PER_USEC 4
    #elif F_CPU == 16000000
    #define PULSEIN_LOOPS_PER_USEC 1
    #elif F_CPU == 8000000
    #define PULSEIN_LOOPS_PER_USEC 1
    #elif F_CPU == 4000000
    #define PULSEIN_LOOPS_PER_USEC 1
    #elif F_CPU == 2000000
    #define PULSEIN_LOOPS_PER_USEC 1
    #endif
    
    #if defined(KINETISK)
    uint32_t pulseIn_high(volatile uint8_t *reg, uint32_t timeout)
    {
    	uint32_t timeout_count = timeout * PULSEIN_LOOPS_PER_USEC;
    	uint32_t usec_start, usec_stop;
    
    	// wait for any previous pulse to end
    	while (*reg) {
    		if (--timeout_count == 0) return 0;
    	}
    	// wait for the pulse to start
    	while (!*reg) {
    		if (--timeout_count == 0) return 0;
    	}
    	usec_start = micros();
    	// wait for the pulse to stop
    	while (*reg) {
    		if (--timeout_count == 0) return 0;
    	}
    	usec_stop = micros();
    	return usec_stop - usec_start;
    }
    
    uint32_t pulseIn_low(volatile uint8_t *reg, uint32_t timeout)
    {
    	uint32_t timeout_count = timeout * PULSEIN_LOOPS_PER_USEC;
    	uint32_t usec_start, usec_stop;
    	
    	// wait for any previous pulse to end
    	while (!*reg) {
    		if (--timeout_count == 0) return 0;
    	}
    	// wait for the pulse to start
    	while (*reg) {
    		if (--timeout_count == 0) return 0;
    	}
    	usec_start = micros();
    	// wait for the pulse to stop
    	while (!*reg) {
    		if (--timeout_count == 0) return 0;
    	}
    	usec_stop = micros();
    	return usec_stop - usec_start;
    }
    
    // TODO: an inline version should handle the common case where state is const
    uint32_t pulseIn(uint8_t pin, uint8_t state, uint32_t timeout)
    {
    	if (pin >= CORE_NUM_DIGITAL) return 0;
    	if (state) return pulseIn_high(portInputRegister(pin), timeout);
    	return pulseIn_low(portInputRegister(pin), timeout);;
    }
    
    #elif defined(KINETISL)
    // For TeencyLC need to use mask on the input register as the register is shared by several IO pins
    uint32_t pulseIn_high(volatile uint8_t *reg, uint8_t mask, uint32_t timeout)
    {
    	uint32_t timeout_count = timeout * PULSEIN_LOOPS_PER_USEC;
    	uint32_t usec_start, usec_stop;
    	// wait for any previous pulse to end
    	while (*reg & mask) {
    		if (--timeout_count == 0) return -1;
    	}
    	// wait for the pulse to start
    	while (!(*reg & mask)) {
    		if (--timeout_count == 0) return 0;
    	}
    	usec_start = micros();
    	// wait for the pulse to stop
    	while (*reg & mask) {
    		if (--timeout_count == 0) return 0;
    	}
    	usec_stop = micros();
    	return usec_stop - usec_start;
    }
    
    uint32_t pulseIn_low(volatile uint8_t *reg, uint8_t mask, uint32_t timeout)
    {
    	uint32_t timeout_count = timeout * PULSEIN_LOOPS_PER_USEC;
    	uint32_t usec_start, usec_stop;
    	
    	// wait for any previous pulse to end
    	while (!(*reg & mask)) {
    		if (--timeout_count == 0) return 0;
    	}
    	// wait for the pulse to start
    	while (*reg & mask) {
    		if (--timeout_count == 0) return 0;
    	}
    	usec_start = micros();
    	// wait for the pulse to stop
    	while (!(*reg & mask)) {
    		if (--timeout_count == 0) return 0;
    	}
    	usec_stop = micros();
    	return usec_stop - usec_start;
    }
    
    // TODO: an inline version should handle the common case where state is const
    uint32_t pulseIn(uint8_t pin, uint8_t state, uint32_t timeout)
    {
    	if (pin >= CORE_NUM_DIGITAL) return 0;
    	if (state) return pulseIn_high(portInputRegister(pin), digitalPinToBitMask(pin), timeout);
    	return pulseIn_low(portInputRegister(pin), digitalPinToBitMask(pin), timeout);;
    }
    #endif
    Mass pin toggling code
    Code:
    /* 
     *  Simple Pin Test for Teensy Pro Extended GPIO
     *  Public Domain
    */
    
    void setup() {
      Serial.begin(115200);
      while (!Serial){}                  // Wait for USB
      Serial.println("*** Starting new pin test ***");
    
      for( uint8_t a = 0; a <= 99; a++){  // Initialize all new pins as outputs
        Serial.print(a);
        pinMode(a, OUTPUT);
        Serial.println(" - Intialized");
      }
    
    }
    
    
    
    void loop() {
      
      for( uint8_t a = 0; a <= 99; a++){ // Turn all new pins on
        digitalWrite(a, HIGH);   
      }
      Serial.println("ON");
      delay(750);
    
      
      for( uint8_t a = 0; a <= 99; a++){ // Turn all new pins off
        digitalWrite(a, LOW); 
      }
      Serial.println("     --OFF");
      delay(750);
      
    }

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