manitou
Senior Member+
I did some more SPI tests with SDK's LPSPI3 with FIFO and with DMA. The initial mbed-os lib SPI tests were yielding less than one megabit/second. With the FIFO, SPI data rates are approaching the SPI CLK speed (see table in post #1). CMSIS DMA example is slower than FIFO test because of 960 ns gap between bytes. With scope, fastest SPI CLK observed was 16 MHz. DMA buffers are in non-cacheable memory. For FIFO test, hardware is driving the SPI CS pin.
LPSPI is being clocked at 32.7mhz, max SPI CLK will be 32.7/2. Data sheet says absolute max for LP SPI CLK is 30 mhz.
LPSPI is being clocked at 32.7mhz, max SPI CLK will be 32.7/2. Data sheet says absolute max for LP SPI CLK is 30 mhz.
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