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Thread: Teensy 4? testing mbed NXP MXRT1050-EVKB (600 Mhz M7)

  1. #126
    Senior Member PaulStoffregen's Avatar
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    Is that a Rigol 1000Z series scope?

    Those are at most 100 MHz bandwidth, and have 150 MHz probes, right?

  2. #127
    Senior Member+ manitou's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    Is that a Rigol 1000Z series scope?

    Those are at most 100 MHz bandwidth, and have 150 MHz probes, right?
    Yep. NXP LPSPI/DMA configuration also might still need tuning ... I'll wait for Teensy 4 before spending more cycles tuning the NXP eval board LPSPI.

  3. #128
    Senior Member PaulStoffregen's Avatar
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    Pretty sure the key to high sustained LPSPI throughput for a larger block of data is configuring a big frame size in TCR. It's on my list to do soon. Right now dealing with the finer points of USB VBUS detection and dynamically reprogramming the LDO power supply settings....

  4. #129
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    Since I couldn't get the basic spi_interrupt example running on the 1052 board decided to give the basic quadrature encoder/decoder example a try and compare it to what I got from a T3.5 using the encoder library. For this initial test I use a 12v uxcell. Both gave me pretty much the same values at 12v, approximately 4400. Going to be a little more scientific about this in the next post as I just want to see if the example worked. There are a couple of nice features they add.

  5. #130
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    As a follow on to post #129, this is a better comparison between values obtained between the 1052 and a T3.5 based on a average of several readings of 10 seconds each:
    Code:
    Volts	 1052	     3.5
      5     21,801     21,155  (counts)
    7.5     32,104     32,009
     10     42,833     43,262
    Since I don't have a digital power supply some of the differences between the 1052 and the T3.5 could be due repeatability in setting the supply voltage to the motor.

  6. #131
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    For some strange reason I still can not get the lspi_interrupt example to work - just hangs. So, finally dug out my scope from storage and think I figured out how to use it again. I played around with the example file and looked at clock and mosi. The clock freq was at 262Mhz and ran the test with a SPI rate of 80Mhz. I am posting the photo but not sure its right. Can someone give me a sanity check. I did make the modifications to the pad configurations, and used delays of 100ns:
    Click image for larger version. 

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    Bottom trace is the clock and top trace is mosi.

    Thanks
    Mike

    EDIT: just as a fyi the scope is a hantex dso5102P (100Mhz). There is a hack to get it up to 200Mhz but haven't done it yet. If you all think its worth it I will give it a try.

  7. #132
    Senior Member+ manitou's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    Pretty sure the key to high sustained LPSPI throughput for a larger block of data is configuring a big frame size in TCR. It's on my list to do soon. Right now dealing with the finer points of USB VBUS detection and dynamically reprogramming the LDO power supply settings....
    Re: tuning LPSPI
    On the non-DMA SDK example with max SPI CLK 65.45mhz/2 and requesting SPI CLK of 40 mhz, SDK example sets DIV in CCR to 0, and calculates DBT to 0. Scope shows SPI CLK at 31.2 MHz. With FIFO high-water mark at 14 (lower ISR overhead), data rate is 14.4 mbs. Reducing the high-water mark to 8 increases data rate to 18.8 mbs. Finally, increasing the SPI frame size from 8-bits to 32-bits in TCR, the data rate increases to 30.4 mbs, getting close to SPI CLK rate. I haven't tested the DMA version with 32-bit frames presumably it would benefit from 32-bit frames.

  8. #133
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    Out of curiosity I ported the T3.0 Slave Library to run on the T3.2 and attached it the 1052 board using example master interrupt from the SDk. To get it work I did have reduce the framesize to 16, SPI clock to 20Mhz and the transfer size to 256 (limitation of the slave library). Data did come across from the 1052 to the T3.2 with the following results:
    Code:
                     33222222222211111111110000000000
                     10987654321098765432109876543210
                     --------------------------------
    SPIO_MCR:        00000000000000000000000000000000
    SPIO_CTAR_SLAVE: 01111000000000000000000000000000
    SPI0_SR:         01000010000000000000000000000000
    SPI0_RSER:       00000000000000100000000000000000
    
    Frame Size:      16
    Data Length:     256
    Packets:         1
    Bytes Sent:      512
    Time Elapsed:    155
    uSecs/Byte:      0.30
    Mbps:            3.30
    From the 1052 side, using modified code from @manitou:
    Code:
    SPI CLK 20000000   master clock 261818172 261818172
    fifo 16  watermark 8
    txcount 256 257 us  15937 kbs
    However the data printed didn't come over in sequential order - have to figure that one out. Been testing speeds and waveform but wanted to see if data transfers were actually working correctly

  9. #134
    Senior Member+ manitou's Avatar
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    Quote Originally Posted by mjs513 View Post
    However the data printed didn't come over in sequential order - have to figure that one out. Been testing speeds and waveform but wanted to see if data transfers were actually working correctly
    If you are not using 8-bit frame size, then you may have to worry about byte order. Conveniently, the 1052 LPSPI has a control bit to re-order bytes, BYSW in TCR.

  10. #135
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    Quote Originally Posted by PaulStoffregen View Post
    I'm always amazed the sheer volume of extra stuff to read just to figure out what anything really does. I suppose programmers who write code in that style feel it's good practice. Or maybe NXP has corporate requirements documents & standards which require all code written & formatted a certain way? I'm sure it's all done with the best of intentions, but the end result is an excessive amount of verbiage to sift though, just to figure out what anything actually does.

    I really don't like that highly verbose style. My preference could be summed up as "less is more".
    Amen, brother!

  11. #136
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    If you want to try the T3.2 slave here is the zip:Teensy-3.0-SPI-Master---Slave.zip

    EDIT: Just tried the slave on a T3.5 and it ran - pretty much gave me the same results
    Last edited by mjs513; 12-06-2018 at 08:18 PM.

  12. #137
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    Changed everything to go with 8 bit frame size as a second test, this is what is happening
    Code:
    data[0]: 231
    data[1]: 232
    data[2]: 233
    data[3]: 234
    data[4]: 235
    data[5]: 236
    data[6]: 237
    data[7]: 238
    data[8]: 239
    data[9]: 240
    data[10]: 241
    data[11]: 242
    data[12]: 243
    data[13]: 240
    data[14]: 244
    data[15]: 245
    data[16]: 246
    data[17]: 247
    data[18]: 248
    data[19]: 249
    data[20]: 250
    data[21]: 251
    data[22]: 252
    data[23]: 253
    data[24]: 254
    data[25]: 255
    data[26]: 252
    data[27]: 13
    data[28]: 14
    data[29]: 15
    data[30]: 12
    data[31]: 16
    data[32]: 17
    data[33]: 18
    After this it continues sequentially. Have a funny feeling it may be on the Teensy slave side.

    EDIT: Yep - problem was on the slave side. Had to add 1 microsecond delay to the following function:
    Code:
    void T3SPI::rx16(volatile uint16_t *dataIN, int length){
    	dataIN[dataPointer] = SPI0_POPR;
    	dataPointer++;
    	if (dataPointer == length){
    		dataPointer=0;
    		packetCT++;
    		delay(1);
    	}
    	SPI0_SR |= SPI_SR_RFDF;
    }
    Not sure if there is a better way to accomplish this.
    Last edited by mjs513; 12-06-2018 at 08:59 PM.

  13. #138
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    Just a followup to my SPI testing using I teensy as a slave. I attached a T3.5 and had set the 1052 to transmit at 60Mhz - data came across correctly. Was a bit surprised at this - but to make it work I had to overclock the T3.5 to 168Mhz, at 120Mhz would get data errors.

    Code:
    1052 settings:
    SPI CLK 60000000   master clock 261818172 261818172
    fifo 16  watermark 8
    txcount 256 121 us  33851 kbs

  14. #139
    Senior Member+ manitou's Avatar
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    In the latest version of EVKB SDK, mbedtls and wolfssl are using DCP to accelerate AES and SHA -- about a 3x speedup. And with FreeRTOS included in SDK, the low power app is available, runs MCU at 600, 528, 132, or 24 MHz.
    https://www.nxp.com/docs/en/applicat...te/AN12094.pdf

    I measured milliamps while running the app on my EVKB board, and the results are in post #1
    Last edited by manitou; 12-09-2018 at 08:54 PM.

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