Teensy 4.0 (hypothetical) pin assignments

[PaulStoffregen]

Ok, let's try talking about which 24 of the iMXRT's 97 available I/O pins to (hypothetically) use for a Teensy LC/3.2 form factor board. And possibly 8-12 extras to bring to pads on the bottom side.

First, one important ground rule. Do NOT suggest a larger form factor, high density connectors, or ANY other ideas for more than 24 pins! Seriously, don't even bring this up (as has happened over and over). I will lock and maybe delete this thread if we get sidetracked. A larger form factor may happen in the future, but for this thread the only subject up for discussion is *which* 24 (plus 8-12 bottom side pads) of the 97 pins to choose. For this thread, the topic is the difficult trade-off of which 73 pins do NOT get to route to the 24 breadboard-friendly outside pins!

I've already removed the 6 pins for the SD card, 12 pins for the QSPI flash memory, and 9 pins for programming & boot. Please disregard the FLEXSPI and USDHC features, since those have already been reserved (and on special ports which can be 1.8V without impacting 3.3V signals for the rest of the chip).

Here are the 97 possible pins and their capabilities. You can see on the far right I've already started to flag some pins as very likely to be used, but at this point no decisions are set in stone (or FR4 fiberglass...)

Name      BGA  Power  Def  Analog       ATL0            ALT1            ALT2            ALT3            ALT4            ALT5            ALT6            ALT7
----      ---  -----  ---  ------       ----            ----            ----            ----            ----            ----            ----            ----
AD_B0_00  M14  GPIO   ALT5              PWM2_A3         XBAR_INOUT14    REF_CLK_32K     USB_OTG2_ID     I2C1_SCLS       GPIO1:0         USDHC1_RESET_B  SPI3_SCK
AD_B0_01  H10  GPIO   ALT5              PWM2_B3         XBAR_INOUT15    REF_CLK_24M     USB_OTG1_ID     I2C1_SDAS       GPIO1:1         EWM_OUT_B       SPI3_MOSI
AD_B0_02  M11  GPIO   ALT5              CAN2_TX         XBAR_INOUT16    UART6_TX        USB_OTG1_PWR    PWM1_X0         GPIO1:2         I2C1_HREQ       SPI3_MISO
AD_B0_03  G11  GPIO   ALT5              CAN2_RX         XBAR_INOUT17    UART6_RX        USB_OTG1_OC     PWM1_X1         GPIO1:3         REF_CLK_24M     SPI3_CS0
AD_B0_12  K14  GPIO   ALT5  A1:1        I2C4_SCL        CCM_PMIC_READY  UART1_TX        WDOG2_B         PWM1_X2         GPIO1:12        ENET1588_OUT1   -
AD_B0_13  L14  GPIO   ALT5  A1:2        I2C4_SDA        GPT1_CLK        UART1_RX        EWM_OUT_B       PWM1_X3         GPIO1:13        ENET1588_IN1    REF_CLK_24M
AD_B0_14  H14  GPIO   ALT5  A1:3        USB_OTG2_OC     XBAR_IN24       UART1_CTS       ENET1588_OUT0   CSI_VSYNC       GPIO1:14        CAN2_TX         WDOG1_ANY
AD_B0_15  L10  GPIO   ALT5  A1:4        USB_OTG2_PWR    XBAR_IN25       UART1_RTS       ENET1588_IN0    CSI_HSYNC       GPIO1:15        CAN2_RX         WDOG1_RESET_B_DEB
AD_B1_00  J11  GPIO   ALT5  A1:5,A2:5   USB_OTG2_ID     QTIMER3_TIMER0  UART2_CTS       I2C1_SCL        WDOG1_B         GPIO1:16        USDHC1_WP       KPP_ROW7        Arduino
AD_B1_01  K11  GPIO   ALT5  A1:6,A2:6   USB_OTG1_PWR    QTIMER3_TIMER1  UART2_RTS       I2C1_SDA        CCM_PMIC_READY  GPIO1:17        USDHC1_VSELECT  KPP_COL7        Arduino
AD_B1_02  L11  GPIO   ALT5  A1:7,A2:7   USB_OTG1_ID     QTIMER3_TIMER2  UART2_TX        SPDIF_OUT       ENET1588_OUT2   GPIO1:18        USDHC1_CD_B     KPP_ROW6        Arduino
AD_B1_03  M12  GPIO   ALT5  A1:8,A2:8   USB_OTG1_OC     QTIMER3_TIMER3  UART2_RX        SPDIF_IN        ENET1588_IN2    GPIO1:19        USDHC2_CD_B     KPP_COL6        Arduino
AD_B1_04  L12  GPIO   ALT5  A1:9,A2:9   FLEXSPI_B_DATA3 ENET_MDC        UART3_CTS       SPDIF_SR_CLK    CSI_PIXCLK      GPIO1:20        USDHC2_DATA0    KPP_ROW5
AD_B1_05  K12  GPIO   ALT5  A1:10,A2:10 FLEXSPI_B_DATA2 ENET_MDIO       UART3_RTS       SPDIF_OUT       CSI_MCLK        GPIO1:21        USDHC2_DATA1    KPP_COL5
AD_B1_06  J12  GPIO   ALT5  A1:11,A2:11 FLEXSPI_B_DATA1 I2C3_SDA        UART3_TX        SPDIF_LOCK      CSI_VSYNC       GPIO1:22        USDHC2_DATA2    KPP_ROW4        Arduino
AD_B1_07  K10  GPIO   ALT5  A1:12,A2:12 FLEXSPI_B_DATA0 I2C3_SCL        UART3_RX        SPDIF_EXT_CLK   CSI_HSYNC       GPIO1:23        USDHC2_DATA3    KPP_COL4        Arduino
AD_B1_08  H13  GPIO   ALT5  A1:13,A2:13 FLEXSPI_A_SS1_B PWM4_A0         CAN1_TX         CCM_PMIC_READY  CSI_DATA09      GPIO1:24        USDHC2_CMD      KPP_ROW3        Arduino
AD_B1_09  M13  GPIO   ALT5  A1:14,A2:14 FLEXSPI_A_DQS   PWM4_A1         CAN1_RX         SAI1_MCLK       CSI_DATA08      GPIO1:25        USDHC2_CLK      KPP_COL3        Arduino
AD_B1_10  L13  GPIO   ALT5  A1:15,A2:15 FLEXSPI_A_DATA3 WDOG1_B         UART8_TX        SAI1_RX_SYNC    CSI_DATA07      GPIO1:26        USDHC2_WP       KPP_ROW2        Arduino
AD_B1_11  J13  GPIO   ALT5  A1:0,A2:0   FLEXSPI_A_DATA2 EWM_OUT_B       UART8_RX        SAI1_RX_BCLK    CSI_DATA06      GPIO1:27        USDHC2_RESET_B  KPP_COL2        Arduino
AD_B1_12  H12  GPIO   ALT5  A2:1        FLEXSPI_A_DATA1 ACMP_OUT00      SPI3_PCS0       SAI1_RX0        CSI_DATA05      GPIO1:28        USDHC2_DATA4    KPP_ROW1                Bottom pad
AD_B1_13  H11  GPIO   ALT5  A2:2        FLEXSPI_A_DATA0 ACMP_OUT01      SPI3_MISO       SAI1_TX0        CSI_DATA04      GPIO1:29        USDHC2_DATA5    KPP_COL1                Bottom pad
AD_B1_14  G12  GPIO   ALT5  A2:3        FLEXSPI_A_SCLK  ACMP_OUT02      SPI3_MOSI       SAI1_TX_BCLK    CSI_DATA03      GPIO1:30        USDHC2_DATA6    KPP_ROW0                Bottom pad
AD_B1_15  J14  GPIO   ALT5  A2:4        FLEXSPI_A_SS0_B ACMP_OUT03      SPI3_SCK        SAI1_TX_SYNC    CSI_DATA02      GPIO1:31        USDHC2_DATA7    KPP_COL0                Bottom pad

Name      BGA  Power  Def  Analog       ATL0            ALT1            ALT2            ALT3            ALT4            ALT5            ALT6            ALT7
----      ---  -----  ---  ------       ----            ----            ----            ----            ----            ----            ----            ----
B0_00     D7   GPIO   ALT5              LCD_CLK         QTIMER1_TIMER0  MQS_RIGHT       SPI4_CS0        FlexIO2:0       GPIO2:0         SEMC_CSX1       -               Arduino 10
B0_01     E7   GPIO   ALT5              LCD_ENABLE      QTIMER1_TIMER1  MQS_LEFT        SPI4_MISO       FlexIO2:1       GPIO2:1         SEMC_CSX2       -               Arduino 12
B0_02     E8   GPIO   ALT5              LCD_HSYNC       QTIMER1_TIMER2  CAN1_TX         SPI4_MOSI       FlexIO2:2       GPIO2:2         SEMC_CSX3       -               Arduino 11
B0_03     D8   GPIO   ALT5              LCD_VSYNC       QTIMER2_TIMER0  CAN1_RX         SPI4_SCK        FlexIO2:3       GPIO2:3         WDOG2_RESET_B_DEB               Arduino 13
B0_04     C8   GPIO   ALT5              LCD_DATA00      QTIMER2_TIMER1  I2C2_SCL        ARM_TRACE0      FlexIO2:4       GPIO2:4         SRC_BOOT_CFG00
B0_05     B8   GPIO   ALT5              LCD_DATA01      QTIMER2_TIMER2  I2C2_SDA        ARM_TRACE1      FlexIO2:5       GPIO2:5         SRC_BOOT_CFG01
B0_06     A8   GPIO   ALT5              LCD_DATA02      QTIMER3_TIMER0  PWM2_A0         ARM_TRACE2      FlexIO2:6       GPIO2:6         SRC_BOOT_CFG02
B0_07     A9   GPIO   ALT5              LCD_DATA03      QTIMER3_TIMER1  PWM2_B0         ARM_TRACE3      FlexIO2:7       GPIO2:7         SRC_BOOT_CFG03
B0_08     B9   GPIO   ALT5              LCD_DATA04      QTIMER3_TIMER2  PWM2_A1         UART3_TX        FlexIO2:8       GPIO2:8         SRC_BOOT_CFG04
B0_09     C9   GPIO   ALT5              LCD_DATA05      QTIMER4_TIMER0  PWM2_B1         UART3_RX        FlexIO2:9       GPIO2:9         SRC_BOOT_CFG05
B0_10     D9   GPIO   ALT5              LCD_DATA06      QTIMER4_TIMER1  PWM2_A2         SAI1_TX3_RX1    FlexIO2:10      GPIO2:10        SRC_BOOT_CFG06
B0_11     A10  GPIO   ALT5              LCD_DATA07      QTIMER4_TIMER2  PWM2_B2         SAI1_TX2_RX2    FlexIO2:11      GPIO2:11        SRC_BOOT_CFG07
B0_12     C10  GPIO   ALT5              LCD_DATA08      XBAR_INOUT10    ARM_TRACE_CLK   SAI1_TX1_RX3    FlexIO2:12      GPIO2:12        SRC_BOOT_CFG08
B0_14     E10  GPIO   ALT5              LCD_DATA10      XBAR_INOUT12    ARM_CM7_EVENT0  SAI1_RX_SYNC    FlexIO2:14      GPIO2:14        SRC_BOOT_CFG10
B0_15     E11  GPIO   ALT5              LCD_DATA11      XBAR_INOUT13    ARM_CM7_EVENT1  SAI1_RX_BCLK    FlexIO2:15      GPIO2:15        SRC_BOOT_CFG11
B1_00     A11  GPIO   ALT5              LCD_DATA12      XBAR_INOUT14    UART4_TX        SAI1_RX_DATA    FlexIO2:16      GPIO2:16        PWM1_A3
B1_01     B11  GPIO   ALT5              LCD_DATA13      XBAR_INOUT15    UART4_RX        SAI1_TX_DATA    FlexIO2:17      GPIO2:17        PWM1_B3
B1_02     C11  GPIO   ALT5              LCD_DATA14      XBAR_INOUT16    SPI4_CS2        SAI1_TX_BCLK    FlexIO2:18      GPIO2:18        PWM2_A3
B1_03     D11  GPIO   ALT5              LCD_DATA15      XBAR_INOUT17    SPI4_CS1        SAI1_TX_SYNC    FlexIO2:19      GPIO2:19        PWM2_B3
B1_04     E12  GPIO   ALT5              LCD_DATA16      SPI4_CS0        CSI_DATA15      ENET_RX_DATA0   FlexIO2:20      GPIO2:20        -               -
B1_05     D12  GPIO   ALT5              LCD_DATA17      SPI4_MISO       CSI_DATA14      ENET_RX_DATA1   FlexIO2:21      GPIO2:21        -               -
B1_06     C12  GPIO   ALT5              LCD_DATA18      SPI4_MOSI       CSI_DATA13      ENET_RX_EN      FlexIO2:22      GPIO2:22        -               -
B1_07     B12  GPIO   ALT5              LCD_DATA19      SPI4_SCK        CSI_DATA12      ENET_TX_DATA0   FlexIO2:23      GPIO2:23        -               -
B1_08     A12  GPIO   ALT5              LCD_DATA20      QTIMER1_TIMER3  CSI_DATA11      ENET_TX_DATA1   FlexIO2:24      GPIO2:24        CAN2_TX         -
B1_09     A13  GPIO   ALT5              LCD_DATA21      QTIMER2_TIMER3  CSI_DATA10      ENET_TX_EN      FlexIO2:25      GPIO2:25        CAN2_RX         -
B1_10     B13  GPIO   ALT5              LCD_DATA22      QTIMER3_TIMER3  CSI_DATA00      ENET_TX_CLK     FlexIO2:26      GPIO2:26        ENET_REF_CLK    -
B1_11     C13  GPIO   ALT5              LCD_DATA23      QTIMER4_TIMER3  CSI_DATA01      ENET_RX_ER      FlexIO2:27      GPIO2:27        SPI4_CS3        -
B1_12     D13  GPIO   ALT5              -               UART5_TX        CSI_PIXCLK      ENET1588_IN0    FlexIO2:28      GPIO2:28        USDHC1_CD_B     -
B1_13     D14  GPIO   ALT5              WDOG1_B         UART5_RX        CSI_VSYNC       ENET1588_OUT0   FlexIO2:29      GPIO2:29        USDHC1_WP       -
B1_14     C14  GPIO   ALT5              ENET_MDC        PWM4_A2         CSI_HSYNC       XBAR_IN02       FlexIO2:30      GPIO2:30        USDHC1_VSELECT  -
B1_15     B14  GPIO   ALT5              ENET_MDIO       PWM4_A3         CSI_MCLK        XBAR_IN03       FlexIO2:31      GPIO2:31        USDHC1_RESET_B  -

Name      BGA  Power  Def  Analog       ATL0            ALT1            ALT2            ALT3            ALT4            ALT5            ALT6            ALT7
----      ---  -----  ---  ------       ----            ----            ----            ----            ----            ----            ----            ----
EMC_00    E3   EMC    ALT5              SEMC_DATA00     PWM4_A0         SPI2_SCK        XBAR_IN02       FlexIO1:0       GPIO4:0         USB_PHY1_TSTI_TX_LS_MODE
EMC_01    F3   EMC    ALT5              SEMC_DATA01     PWM4_B0         SPI2_CS0        XBAR_IN03       FlexIO1:1       GPIO4:1         USB_PHY1_TSTI_TX_HS_MODE
EMC_02    F4   EMC    ALT5              SEMC_DATA02     PWM4_A1         SPI2_MOSI       XBAR_INOUT04    FlexIO1:2       GPIO4:2         USB_PHY1_TSTI_TX_DN
EMC_03    G4   EMC    ALT5              SEMC_DATA03     PWM4_B1         SPI2_MISO       XBAR_INOUT05    FlexIO1:3       GPIO4:3         USB_PHY1_TSTO_RX_SQUELCH
EMC_04    F2   EMC    ALT5              SEMC_DATA04     PWM4_A2         SAI2_TX0        XBAR_INOUT06    FlexIO1:4       GPIO4:4         USB_PHY1_TSTO_RX_DISCON_DET
EMC_05    G5   EMC    ALT5              SEMC_DATA05     PWM4_B2         SAI2_TX_SYNC    XBAR_INOUT07    FlexIO1:5       GPIO4:5         USB_PHY1_TSTO_RX_HS_RXD
EMC_06    H5   EMC    ALT5              SEMC_DATA06     PWM2_A0         SAI2_TX_BCLK    XBAR_INOUT08    FlexIO1:6       GPIO4:6         USB_PHY2_TSTO_RX_FS_RXD
EMC_07    H4   EMC    ALT5              SEMC_DATA07     PWM2_B0         SAI2_MCLK       XBAR_INOUT09    FlexIO1:7       GPIO4:7         USB_PHY1_TSTO_RX_FS_RXD
EMC_08    H3   EMC    ALT5              SEMC_DM0        PWM2_A1         SAI2_RX0        XBAR_INOUT17    FlexIO1:8       GPIO4:8         USB_PHY1_TSTI_TX_DP
EMC_09    C2   EMC    ALT5              SEMC_ADDR00     PWM2_B1         SAI2_RX_SYNC    CAN2_TX         FlexIO1:9       GPIO4:9         USB_PHY1_TSTI_TX_EN
EMC_10    G1   EMC    ALT5              SEMC_ADDR01     PWM2_A2         SAI2_RX_BCLK    CAN2_RX         FlexIO1:10      GPIO4:10        USB_PHY1_TSTI_TX_HIZ
EMC_11    G3   EMC    ALT5              SEMC_ADDR02     PWM2_B2         I2C4_SDA        USDHC2_RESET_B  FlexIO1:11      GPIO4:11        USB_PHY2_TSTO_RX_HS_RXD
EMC_12    H1   EMC    ALT5              SEMC_ADDR03     XBAR_IN24       I2C4_SCL        USDHC1_WP       PWM1_A3         GPIO4:12        USB_PHY1_TSTO_PLL_CLK20DIV
EMC_13    A6   EMC    ALT5              SEMC_ADDR04     XBAR_IN25       UART3_TX        MQS_RIGHT       PWM1_B3         GPIO4:13        USB_PHY2_TSTO_PLL_CLK20DIV
EMC_14    B6   EMC    ALT5              SEMC_ADDR05     XBAR_INOUT19    UART3_RX        MQS_LEFT        SPI2_CS1        GPIO4:14        USB_PHY2_TSTO_RX_SQUELCH
EMC_15    B1   EMC    ALT5              SEMC_ADDR06     XBAR_IN20       UART3_CTS       SPDIF_OUT       QTIMER3_TIMER0  GPIO4:15        USB_PHY2_TSTO_RX_DISCON_DET
EMC_16    A5   EMC    ALT5              SEMC_ADDR07     XBAR_IN21       UART3_RTS       SPDIF_IN        QTIMER3_TIMER1  GPIO4:16
EMC_17    A4   EMC    ALT5              SEMC_ADDR08     PWM4_A3         UART4_CTS       CAN1_TX         QTIMER3_TIMER2  GPIO4:17
EMC_18    B2   EMC    ALT5              SEMC_ADDR09     PWM4_B3         UART4_RTS       CAN1_RX         QTIMER3_TIMER3  GPIO4:18        SNVS_VIO_5_CTL
EMC_19    B4   EMC    ALT5              SEMC_ADDR11     PWM2_A3         UART4_TX        ENET_RX_DATA1   QTIMER2_TIMER0  GPIO4:19        SNVS_VIO_5_B
EMC_20    A3   EMC    ALT5              SEMC_ADDR12     PWM2_B3         UART4_RX        ENET_RX_DATA0   QTIMER2_TIMER1  GPIO4:20
EMC_21    C1   EMC    ALT5              SEMC_BA0        PWM3_A3         I2C3_SDA        ENET_TX_DATA1   QTIMER2_TIMER2  GPIO4:21
EMC_22    F1   EMC    ALT5              SEMC_BA1        PWM3_B3         I2C3_SCL        ENET_TX_DATA0   QTIMER2_TIMER3  GPIO4:22
EMC_23    G2   EMC    ALT5              SEMC_ADDR10     PWM1_A0         UART5_TX        ENET_RX_EN      GPT1_CAPTURE2   GPIO4:23
EMC_24    D3   EMC    ALT5              SEMC_CAS        PWM1_B0         UART5_RX        ENET_TX_EN      GPT1_CAPTURE1   GPIO4:24
EMC_25    D2   EMC    ALT5              SEMC_RAS        PWM1_A1         UART6_TX        ENET_TX_CLK     ENET_REF_CLK    GPIO4:25
EMC_26    B3   EMC    ALT5              SEMC_CLK        PWM1_B1         UART6_RX        ENET_RX_ER      FlexIO1:12      GPIO4:26
EMC_27    A2   EMC    ALT5              SEMC_CKE        PWM1_A2         UART5_RTS       SPI1_SCK        FlexIO1:13      GPIO4:27
EMC_28    D1   EMC    ALT5              SEMC_WE         PWM1_B2         UART5_CTS       SPI1_MOSI       FlexIO1:14      GPIO4:28
EMC_29    E1   EMC    ALT5              SEMC_CS0        PWM3_A0         UART6_RTS       SPI1_MISO       FlexIO1:15      GPIO4:29
EMC_30    C6   EMC    ALT5              SEMC_DATA08     PWM3_B0         UART6_CTS       SPI1_CS0        CSI_DATA23      GPIO4:30
EMC_31    C5   EMC    ALT5              SEMC_DATA09     PWM3_A1         UART7_TX        SPI1_CS1        CSI_DATA22      GPIO4:31
EMC_32    D5   EMC    ALT5              SEMC_DATA10     PWM3_B1         UART7_RX        CCM_PMIC_READY  CSI_DATA21      GPIO3:18
EMC_33    C4   EMC    ALT5              SEMC_DATA11     PWM3_A2         USDHC1_RESET_B  SAI3_RX_DATA    CSI_DATA20      GPIO3:19
EMC_34    D4   EMC    ALT5              SEMC_DATA12     PWM3_B2         USDHC1_VSELECT  SAI3_RX_SYNC    CSI_DATA19      GPIO3:20
EMC_35    E5   EMC    ALT5              SEMC_DATA13     XBAR_INOUT18    GPT1_COMPARE1   SAI3_RX_BCLK    CSI_DATA18      GPIO3:21        USDHC1_CD_B
EMC_36    C3   EMC    ALT5              SEMC_DATA14     XBAR_IN22       GPT1_COMPARE2   SAI3_TX_DATA    CSI_DATA17      GPIO3:22        USDHC1_WP
EMC_37    E4   EMC    ALT5              SEMC_DATA15     XBAR_IN23       GPT1_COMPARE3   SAI3_MCLK       CSI_DATA16      GPIO3:23        USDHC2_WP
EMC_38    D6   EMC    ALT5              SEMC_DM1        PWM1_A3         UART8_TX        SAI3_TX_BCLK    CSI_FIELD       GPIO3:24        USDHC2_VSELECT
EMC_39    B7   EMC    ALT5              SEMC_DQS        PWM1_B3         UART8_RX        SAI3_TX_SYNC    WDOG1_B         GPIO3:25        USDHC2_CD_B
EMC_40    A7   EMC    ALT5              SEMC_RDY        GPT2_CAPTURE2   SPI1_CS2        USB_OTG2_OC     ENET_MDC        GPIO3:26        USDHC2_RESET_B
EMC_41    C7   EMC    ALT5              SEMC_CSX0       GPT2_CAPTURE1   SPI1_CS3        USB_OTG2_PWR    ENET_MDIO       GPIO3:27        USDHC1_VSELECT

[PaulStoffregen]

I'm sure many of these feature names will look familiar. Obviously we want to get as many unique PWM pins as possible, many UART RX & TX pairs, at least a couple I2C SDA & SCL, at least one SPI, CAN bus, and so on.

Here's a little info about the names that aren't similar to Teensy 3.x...

QTIMER is similar to the FTM timers we have today, but focused on the non-PWM uses. The PWM pins are separate timers with so many advanced PWM features it makes the 100 pages of FTM documentation look like an old-school PIC chip! Clearly we want as many of both types of timer pins as we can get.

XBAR allows arbitrary connection to ~120 other signals inside the chip which don't map to any ALT slots on any pins. The 4 quadrature encoders only connect to XBAR, so we definitely want some XBAR signals.

FlexIO is a programmable serial/parallel port. We'll probably use this for ILI9431, maybe efficiently driving WS2812, and other "special" protocols that don't map so nicely onto SPI & UART.

MQS is a special PWM meant for audio output.

SPDIF is, well, for S/PDIF digital audio. Finally we'll have real input, and output without the overhead of Frank's amazing hack to I2S. Of course, we need those 2 signals to get it.

SAI is Serial Audio Interface. While this chip as 3 of them, SAI3 is sort-of dedicated to MQS, so only SAI1 & SAI2 matter. We only use 1 pair of the "SYNC" and "BCLK" signals in the audio library, so there's no need to have both SAI1_RX_SYNC and SAI1_TX_SYNC.

The other point I should bring up is the 42 EMC pins. If *none* of those are used, they remain open for someday adding a SDRAM chip. But with NXP already announcing a iMXRT with 1 Mbyte of RAM, and more chips likely to come in the future, and with pricing pressure from so many other dev boards, I'm pretty sure there won't be any Teensy using the EMC pins for a memory chip.

[WMXZ]

SAI is Serial Audio Interface. While this chip as 3 of them, SAI3 is sort-of dedicated to MQS, so only SAI1 & SAI2 matter. We only use 1 pair of the "SYNC" and "BCLK" signals in the audio library, so there's no need to have both SAI1_RX_SYNC and SAI1_TX_SYNC.

I would not constrain future boards to existing HW.

I would vote for
full SAI1 outside : 9 pins (don't know what SAI1_TX3_RX1 etc means, additional data lines would be very interesting to me)
full USDHC2 (also data0 to data3) : 12 pins inside 4 pins outside

I know this will never be implemented (due to form factor), but I wanted to have may say.

[defragster]

There are 14 pads {w/GND/3.3V} on the T_3.2 bottom. Would this add "possibly 8-12 extras" to those - or is that 8-12 total with none under the MCU?

What of the 5 end pins? Assuming those are gone like the T_3.6 - that has 24 pads on the bottom with none under the MCU

[PaulStoffregen]

full SAI1 outside : 9 pins (don't know what SAI1_TX3_RX1 etc means, additional data lines would be very interesting to me)

There are 10 different SAI1 signals. Like with Teensy 3.x, the transmitter and receiver can run in sync, which means you don't need two different BCLK and SYNC/LRCLK signals.

Running the transmitter and receiver out of sync only makes sense for a very limited set of circumstances, like two different chips both running in master mode from clock sources outside Teensy's control. It's extremely unlikely I'll ever support this in the audio library. Even now, we have pretty limited support for just 1 device in master mode, and using that feature causes the entire audio lib to run in sync with that external clock. There isn't any support for arbitrarily resampling incoming data to Teensy's clock, or to match any other clock.

Unless someone can explain a sensible use case (where code would actually be written) I'm not inclined to have the redundant BCLK and SYNC signals.

The data signals like SAI1_TX3_RX1, SAI1_TX2_RX2, SAI1_TX1_RX3 are unfortunately one of the many hardware details that isn't explained in this first version of the reference manual, despite it weighing in at 3563 pages! My best guess is we get a total of 5 data signals on SAI1 where we can allocate 3 of them to either transmitting or receiving. Internally, the SAI chapter documents 4 transmit and 4 receive. But they clearly didn't bring all 8 to the IOMUX. We get 5, which is still a step up from 4 in Teensy 3.x. Then again, if you want a lot of channels TDM is the way to go.

There are 14 pads {w/GND/3.3V} on the T_3.2 bottom. Would this add "possibly 8-12 extras" to those

Yes, this extra 8-12 on the bottom is anticipating I'll be able to cram pads on the bottom side, very similar to the Teensy 3.x boards.

What of the 5 end pins?[/QUOTE]

The middle 3 will be power and program, and the extra 2 will be special power management pins. As I said, this thread is about choosing 24 specific signals (and choosing 73 to not have on the outside edge). Different groups of 24 provide more of some features but less of others. It's a touch trade-off....

[dauntless89]

At this point I don't have the experience to lend any useful suggestions on specific pins to include or exclude.

Unless several variants optimized for specific roles could be developed (T4-audio, T4-comm board, T4-digital/analog IO, and I know this is as unrealistic as it would be awesome), I would encourage a balanced approach.

I'm sure you know better than I that these things are used in projects of all kinds of different natures, and I expect a balanced I/O configuration would be the best way to keep this iteration of the T4 most relevant to the largest number of existing and potential customers.

[PaulStoffregen]

It is a tough balancing act indeed. I have a few ideas in the works... but I wanted to open it up at least for discussion.

If anyone wants to take a shot at this, reply with the 24 lines you'd choose and maybe some of the reasons why.

[PaulStoffregen]

Here's some of my current thinking on the pins....

First, the analog pins are the easy part. There's only 20 pins with ADC input and 10 need to be picked, where 2 must have an I2C port. I'm leaning towards these 10:

Name      BGA  Power  Def  Analog       ATL0            ALT1            ALT2            ALT3            ALT4            ALT5            ALT6            ALT7
----      ---  -----  ---  ------       ----            ----            ----            ----            ----            ----            ----            ----
AD_B1_00  J11  GPIO   ALT5  A1:5,A2:5   USB_OTG2_ID     QTIMER3_TIMER0  UART2_CTS       I2C1_SCL        WDOG1_B         GPIO1:16        USDHC1_WP       KPP_ROW7        Arduino analog
AD_B1_01  K11  GPIO   ALT5  A1:6,A2:6   USB_OTG1_PWR    QTIMER3_TIMER1  UART2_RTS       I2C1_SDA        CCM_PMIC_READY  GPIO1:17        USDHC1_VSELECT  KPP_COL7        Arduino analog
AD_B1_02  L11  GPIO   ALT5  A1:7,A2:7   USB_OTG1_ID     QTIMER3_TIMER2  UART2_TX        SPDIF_OUT       ENET1588_OUT2   GPIO1:18        USDHC1_CD_B     KPP_ROW6        Arduino analog
AD_B1_03  M12  GPIO   ALT5  A1:8,A2:8   USB_OTG1_OC     QTIMER3_TIMER3  UART2_RX        SPDIF_IN        ENET1588_IN2    GPIO1:19        USDHC2_CD_B     KPP_COL6        Arduino analog
AD_B1_06  J12  GPIO   ALT5  A1:11,A2:11 FLEXSPI_B_DATA1 I2C3_SDA        UART3_TX        SPDIF_LOCK      CSI_VSYNC       GPIO1:22        USDHC2_DATA2    KPP_ROW4        Arduino analog
AD_B1_07  K10  GPIO   ALT5  A1:12,A2:12 FLEXSPI_B_DATA0 I2C3_SCL        UART3_RX        SPDIF_EXT_CLK   CSI_HSYNC       GPIO1:23        USDHC2_DATA3    KPP_COL4        Arduino analog
AD_B1_08  H13  GPIO   ALT5  A1:13,A2:13 FLEXSPI_A_SS1_B PWM4_A0         CAN1_TX         CCM_PMIC_READY  CSI_DATA09      GPIO1:24        USDHC2_CMD      KPP_ROW3        Arduino analog
AD_B1_09  M13  GPIO   ALT5  A1:14,A2:14 FLEXSPI_A_DQS   PWM4_A1         CAN1_RX         SAI1_MCLK       CSI_DATA08      GPIO1:25        USDHC2_CLK      KPP_COL3        Arduino analog
AD_B1_10  L13  GPIO   ALT5  A1:15,A2:15 FLEXSPI_A_DATA3 WDOG1_B         UART8_TX        SAI1_RX_SYNC    CSI_DATA07      GPIO1:26        USDHC2_WP       KPP_ROW2        Arduino analog
AD_B1_11  J13  GPIO   ALT5  A1:0,A2:0   FLEXSPI_A_DATA2 EWM_OUT_B       UART8_RX        SAI1_RX_BCLK    CSI_DATA06      GPIO1:27        USDHC2_RESET_B  KPP_COL2        Arduino analog

This gives 3 serial, 2 I2C, SPDIF, 1 CAN, 2 PWM, 4 QTIMER, and 3 of the 5 signals for I2S.

There are a few options to pick up the other 2 I2S signals. This is the one I like the most, because it give another serial port, 2 more PWM, and we get 2 more XBAR and FlexIO signals.

B1_00     A11  GPIO   ALT5              LCD_DATA12      XBAR_INOUT14    UART4_TX        SAI1_RX_DATA    FlexIO2:16      GPIO2:16        PWM1_A3
B1_01     B11  GPIO   ALT5              LCD_DATA13      XBAR_INOUT15    UART4_RX        SAI1_TX_DATA    FlexIO2:17      GPIO2:17        PWM1_B3

At least one SPI port is needed. There are 5 candidates (and also a 6th, but it's on pins I want to save for Ethernet, so only showing 5 here).

B0_00     D7   GPIO   ALT5              LCD_CLK         QTIMER1_TIMER0  MQS_RIGHT       SPI4_CS0        FlexIO2:0       GPIO2:0         SEMC_CSX1       -
B0_01     E7   GPIO   ALT5              LCD_ENABLE      QTIMER1_TIMER1  MQS_LEFT        SPI4_MISO       FlexIO2:1       GPIO2:1         SEMC_CSX2       -
B0_02     E8   GPIO   ALT5              LCD_HSYNC       QTIMER1_TIMER2  CAN1_TX         SPI4_MOSI       FlexIO2:2       GPIO2:2         SEMC_CSX3       -
B0_03     D8   GPIO   ALT5              LCD_VSYNC       QTIMER2_TIMER0  CAN1_RX         SPI4_SCK        FlexIO2:3       GPIO2:3         WDOG2_RESET_B_DEB

EMC_00    E3   EMC    ALT5              SEMC_DATA00     PWM4_A0         SPI2_SCK        XBAR_IN02       FlexIO1:0       GPIO4:0         USB_PHY1_TSTI_TX_LS_MODE
EMC_01    F3   EMC    ALT5              SEMC_DATA01     PWM4_B0         SPI2_CS0        XBAR_IN03       FlexIO1:1       GPIO4:1         USB_PHY1_TSTI_TX_HS_MODE
EMC_02    F4   EMC    ALT5              SEMC_DATA02     PWM4_A1         SPI2_MOSI       XBAR_INOUT04    FlexIO1:2       GPIO4:2         USB_PHY1_TSTI_TX_DN
EMC_03    G4   EMC    ALT5              SEMC_DATA03     PWM4_B1         SPI2_MISO       XBAR_INOUT05    FlexIO1:3       GPIO4:3         USB_PHY1_TSTO_RX_SQUELCH

AD_B0_00  M14  GPIO   ALT5              PWM2_A3         XBAR_INOUT14    REF_CLK_32K     USB_OTG2_ID     I2C1_SCLS       GPIO1:0         USDHC1_RESET_B  SPI3_SCK
AD_B0_01  H10  GPIO   ALT5              PWM2_B3         XBAR_INOUT15    REF_CLK_24M     USB_OTG1_ID     I2C1_SDAS       GPIO1:1         EWM_OUT_B       SPI3_MOSI
AD_B0_02  M11  GPIO   ALT5              CAN2_TX         XBAR_INOUT16    UART6_TX        USB_OTG1_PWR    PWM1_X0         GPIO1:2         I2C1_HREQ       SPI3_MISO
AD_B0_03  G11  GPIO   ALT5              CAN2_RX         XBAR_INOUT17    UART6_RX        USB_OTG1_OC     PWM1_X1         GPIO1:3         REF_CLK_24M     SPI3_CS0

EMC_27    A2   EMC    ALT5              SEMC_CKE        PWM1_A2         UART5_RTS       SPI1_SCK        FlexIO1:13      GPIO4:27
EMC_28    D1   EMC    ALT5              SEMC_WE         PWM1_B2         UART5_CTS       SPI1_MOSI       FlexIO1:14      GPIO4:28
EMC_29    E1   EMC    ALT5              SEMC_CS0        PWM3_A0         UART6_RTS       SPI1_MISO       FlexIO1:15      GPIO4:29
EMC_30    C6   EMC    ALT5              SEMC_DATA08     PWM3_B0         UART6_CTS       SPI1_CS0        CSI_DATA23      GPIO4:30

AD_B1_12  H12  GPIO   ALT5  A2:1        FLEXSPI_A_DATA1 ACMP_OUT00      SPI3_PCS0       SAI1_RX0        CSI_DATA05      GPIO1:28        USDHC2_DATA4    KPP_ROW1
AD_B1_13  H11  GPIO   ALT5  A2:2        FLEXSPI_A_DATA0 ACMP_OUT01      SPI3_MISO       SAI1_TX0        CSI_DATA04      GPIO1:29        USDHC2_DATA5    KPP_COL1
AD_B1_14  G12  GPIO   ALT5  A2:3        FLEXSPI_A_SCLK  ACMP_OUT02      SPI3_MOSI       SAI1_TX_BCLK    CSI_DATA03      GPIO1:30        USDHC2_DATA6    KPP_ROW0
AD_B1_15  J14  GPIO   ALT5  A2:4        FLEXSPI_A_SS0_B ACMP_OUT03      SPI3_SCK        SAI1_TX_SYNC    CSI_DATA02      GPIO1:31        USDHC2_DATA7    KPP_COL0

Whether to put 1 or 2 of these groups on the 14 outside pins is a good question. Two SPI quick burns up the 14 digital pins, but all of these have some pretty tempting alternate features that could make them worthy of using up the precious 14 digital slots.

So far this is 4 of the 8 serial ports (or 5 if EMC27-EMC30 are chosen for SPI). Here are pins that could be used get some or all of the remaining serial. At least 1 of these needs to be chosen for Arduino pins 0 & 1.

EMC_23    G2   EMC    ALT5              SEMC_ADDR10     PWM1_A0         UART5_TX        ENET_RX_EN      GPT1_CAPTURE2   GPIO4:23
EMC_24    D3   EMC    ALT5              SEMC_CAS        PWM1_B0         UART5_RX        ENET_TX_EN      GPT1_CAPTURE1   GPIO4:24

EMC_25    D2   EMC    ALT5              SEMC_RAS        PWM1_A1         UART6_TX        ENET_TX_CLK     ENET_REF_CLK    GPIO4:25
EMC_26    B3   EMC    ALT5              SEMC_CLK        PWM1_B1         UART6_RX        ENET_RX_ER      FlexIO1:12      GPIO4:26
  ---or---
AD_B0_02  M11  GPIO   ALT5              CAN2_TX         XBAR_INOUT16    UART6_TX        USB_OTG1_PWR    PWM1_X0         GPIO1:2         I2C1_HREQ       SPI3_MISO
AD_B0_03  G11  GPIO   ALT5              CAN2_RX         XBAR_INOUT17    UART6_RX        USB_OTG1_OC     PWM1_X1         GPIO1:3         REF_CLK_24M     SPI3_CS0

AD_B0_12  K14  GPIO   ALT5  A1:1        I2C4_SCL        CCM_PMIC_READY  UART1_TX        WDOG2_B         PWM1_X2         GPIO1:12        ENET1588_OUT1   -
AD_B0_13  L14  GPIO   ALT5  A1:2        I2C4_SDA        GPT1_CLK        UART1_RX        EWM_OUT_B       PWM1_X3         GPIO1:13        ENET1588_IN1    REF_CLK_24M

There are more interesting pins. For example, these 2 would allow the I2S to do 8 channel in or out (and stereo in the other direction). I'm less inclined since you can do 8 channels with TDM (as we have now on Teensy 3.x), though that does limit you to only certain chips with TDM support.

B0_10     D9   GPIO   ALT5              LCD_DATA06      QTIMER4_TIMER1  PWM2_A2         SAI1_TX3_RX1    FlexIO2:10      GPIO2:10        SRC_BOOT_CFG06
B0_11     A10  GPIO   ALT5              LCD_DATA07      QTIMER4_TIMER2  PWM2_B2         SAI1_TX2_RX2    FlexIO2:11      GPIO2:11        SRC_BOOT_CFG07
B0_12     C10  GPIO   ALT5              LCD_DATA08      XBAR_INOUT10    ARM_TRACE_CLK   SAI1_TX1_RX3    FlexIO2:12      GPIO2:12        SRC_BOOT_CFG08

Of course these are so many other pins... we could forgo some of these features to pick up more XBAR and FlexIO pins, or more PWM and QTIMER.

Hopefully this helps get the conversation started. Are there other choices I've missed? Now's the time to comment. Just remember, the limit (for this thread) is 24 pins assigned to the outside edge, and 8-12 more maybe on bottom-side pads if space permits.

[Davidelvig]

I've found the topside capacitive touch pins handy, and am using all that are spared by other protocols.
Are Cap touch pins still in the mix? (more, less, the same?)
How are those designated above?

[PaulStoffregen]

Are Cap touch pins still in the mix?

Sadly, no, the new chip doesn't have any capacitive touch feature.

[WMXZ]

There are 10 different SAI1 signals. Like with Teensy 3.x, the transmitter and receiver can run in sync, which means you don't need two different BCLK and SYNC/LRCLK signals.
Running the transmitter and receiver out of sync only makes sense for a very limited set of circumstances, like two different chips both running in master mode from clock sources outside Teensy's control. It's extremely unlikely I'll ever support this in the audio library. Even now, we have pretty limited support for just 1 device in master mode, and using that feature causes the entire audio lib to run in sync with that external clock. There isn't any support for arbitrarily resampling incoming data to Teensy's clock, or to match any other clock.

Unless someone can explain a sensible use case (where code would actually be written) I'm not inclined to have the redundant BCLK and SYNC signals.

The data signals like SAI1_TX3_RX1, SAI1_TX2_RX2, SAI1_TX1_RX3 are unfortunately one of the many hardware details that isn't explained in this first version of the reference manual, despite it weighing in at 3563 pages! My best guess is we get a total of 5 data signals on SAI1 where we can allocate 3 of them to either transmitting or receiving. Internally, the SAI chapter documents 4 transmit and 4 receive. But they clearly didn't bring all 8 to the IOMUX. We get 5, which is still a step up from 4 in Teensy 3.x. Then again, if you want a lot of channels TDM is the way to go.

The only reason I would see to have both RX and TX sync/clock different is to use teensy as an in-line audio number cruncher with data-rate conversion.
Concerning multiple data lines, at the moment we have two, if we could use at least 4 than one could attach 8 i2s audio devices for volumetric audio recordings. The drawback of using TDM is the 4 times higher bitclock with respect to 4 data channels. I use TDM only when I have a multichannel ADC, but most times I use multiple stereo boards.

To optimize one could have RX sync/clock and 2 of 4 data lines on bottom
(caveat I have not studied your later pinout suggestion)

[PaulStoffregen]

Here's another way of looking at the pin function info. Here I've narrowed it down to 8 digital pins, 10 analog pins, and 19 more which could be in the remaining 6 digital pin positions and maybe some as pads on the back side.

---  ----       ------    ---       ---        ---      ---       ----       ----      ------      -----         ------
Pin  Name       Serial    I2C       SPI        PWM      CAN       SAI1       XBAR      FlexIO      Audio         Analog
---  ----       ------    ---       ---        ---      ---       ----       ----      ------      -----         ------
0    AD_B0_03   UART6_RX            spi3_cs0   PWM1_X1  CAN2_RX              INOUT17
1    AD_B0_02   UART6_TX            spi3_misO  PWM1_X0  CAN2_TX              INOUT16
     B1_01      UART4_RX                       PWM1_B3            1:TX_DATA  INOUT15   FlexIO2:17
     B1_00      UART4_TX                       PWM1_A3            1:RX_DATA  INOUT14   FlexIO2:16
10   B0_00                          SPI4_CS0   QT1_0                                   FlexIO2:0   MQS_RIGHT
11   B0_02                          SPI4_MOSI  QT1_2    CAN1_TX                        FlexIO2:2
12   B0_01                          SPI4_MISO  QT1_1                                   FlexIO2:1   MQS_LEFT
13   B0_03                          SPI4_SCK   QT2_0    CAN1_RX                        FlexIO2:3
---  ----       ------    ---       ---        ---      ---       ----       ----      ------      -----         ------
Pin  Name       Serial    I2C       SPI        PWM      CAN       SAI1       XBAR      FlexIO      Audio         Analog
---  ----       ------    ---       ---        ---      ---       ----       ----      ------      -----         ------
     AD_B1_02   UART2_TX                       QT3_2                                               SPDIF_OUT     A1:7,A2:7
     AD_B1_03   UART2_RX                       QT3_3                                               SPDIF_IN      A1:8,A2:8
16   AD_B1_07   UART3_RX  I2C3_SCL                                                                 SPDIF_EXTCLK  A1:12,A2:12
17   AD_B1_06   UART3_TX  I2C3_SDA                                                                 SPDIF_LOCK    A1:11,A2:11
18   AD_B1_01             I2C1_SDA             QT3_1                                                             A1:6,A2:6
19   AD_B1_00             I2C1_SCL             QT3_0                                                             A1:5,A2:5
     AD_B1_10   UART8_TX                                          1:RX_SYNC                                      A1:15,A2:15
     AD_B1_11   UART8_RX                                          1:RX_BCLK                                      A1:0,A2:0
     AD_B1_08                                  PWM4_A0  CAN1_TX                                                  A1:13,A2:13
     AD_B1_09                                  PWM4_A1  CAN1_RX   1:MCLK                                         A1:14,A2:14
---  ----       ------    ---       ---        ---      ---       ----       ----      ------      -----         ------
Pin  Name       Serial    I2C       SPI        PWM      CAN       SAI1       XBAR      FlexIO      Audio         Analog
---  ----       ------    ---       ---        ---      ---       ----       ----      ------      -----         ------
     EMC_32     UART7_RX                       PWM3_B1
     EMC_31     UART7_TX            spi1_cs1   PWM3_A1
     EMC_23     UART5_TX                       PWM1_A0
     EMC_24     UART5_RX                       PWM1_B0
     B1_03                          SPI4_CS1   PWM2_B3            1:TX_SYNC  INOUT17   FlexIO2:19
     B1_02                          SPI4_CS2   PWM2_A3            1:TX_BCLK  INOUT16   FlexIO2:18
     AD_B0_12   UART1_TX  I2C4_SCL             PWM1_X2                                                           A1:1
     AD_B0_13   UART1_RX  I2C4_SDA             PWM1_X3                                                           A1:2
     EMC_00                         SPI2_SCK   PWM4_A0                       IN02      FlexIO1:0
     EMC_01                         SPI2_CS0   PWM4_B0                       IN03      FlexIO1:1
     EMC_02                         SPI2_MOSI  PWM4_A1                       INOUT04   FlexIO1:2
     EMC_03                         SPI2_MISO  PWM4_B1                       INOUT05   FlexIO1:3
     B0_10                                     PWM2_A2,QT4_1      1:TX3_RX1            FlexIO2:10
     B0_11                                     PWM2_B2,QT4_2      1:TX2_RX2            FlexIO2:11
     B0_12                                                        1:TX1_RX3  INOUT10   FlexIO2:12
     EMC_04                                    PWM4_A2            2:TX_DATA  INOUT06   FlexIO1:4
     EMC_05                                    PWM4_B2            2:TX_SYNC  INOUT07   FlexIO1:5
     EMC_06                                    PWM2_A0            2:TX_BCLK  INOUT08   FlexIO1:6
     EMC_07                                    PWM2_B0            2:MCLK     INOUT09   FlexIO1:7
---  ----       ------    ---       ---        ---      ---       ----       ----      ------      -----         ------
Pin  Name       Serial    I2C       SPI        PWM      CAN       SAI1       XBAR      FlexIO      Audio         Analog
---  ----       ------    ---       ---        ---      ---       ----       ----      ------      -----         ------

[grease_lighting]

I would like to see a full port worth of pins available. 8 and/or 16 bits.

[PaulStoffregen]

The GPIO chapter says this chip doesn't support 8 or 16 bit access, so that probably won't be very useful.

It's also one of the major issues I'm trying to work around for Arduino compatibility with older libraries....

[WMXZ]

Here's another way of looking at the pin function info. Here I've narrowed it down to 8 digital pins, 10 analog pins, and 19 more which could be in the remaining 6 digital pin positions and maybe some as pads on the back side.

The presented pin selection is already very useful for me, so I have no further suggestions

Q: is there already a public available technical reference manual?

[PaulStoffregen]

Q: is there already a public available technical reference manual?

Yup, it's on NXP website. Here's a direct link.

https://www.nxp.com/docs/en/referenc...MXRT1050RM.pdf

3563 pages of light reading.....

It also seems to be riddled with copy-and-paste errors, mostly stuff from other iMX chips.

[KurtE]

Hi Paul,

Looks interesting. So far I have not had the time to try to give alternatives. Been busy trying to understand some issues with a different processor used in the Robotis OpenCR board...

Your straw man looks interesting.
I do like having two SPI ports.

Looking at your last listing, wondering if any of the USARTS have flow control pins RTS/CTS exposed?

[PaulStoffregen]

Looks like only 1 RTS/CTS pair may get exposed. It's looks like that's the price of getting 7 or 8 RX/TX pairs, 2 SPI, a few I2C, full I2S, and lots of other stuff.

[PaulStoffregen]

However, it looks like we can route any of the XBAR pins to become the CTS input for any of the UARTs. Since we use software for RTS, this looks like we could have RTS/CTS flow control on as many ports has we have XBAR pins. The XBAR pins look like they can also be alternate RX pins, but not TX.

But there's another complication. The pinout which maximizes serial ports results in only 4 XBAR pins on the outside 24 signals, and they're shared with 2 of the port RX/TX pins. The SPI2 pins and extra I2S pins (for more than just stereo in/out) all have XBAR. If I bring these to the 24 outside pins, meaning only 4 or 5 serial RX/TX rather than 6 or 7, then we get more XBAR signals (when not using the 2nd SPI or 2nd I2S). So many trade-offs....

[PaulStoffregen]

Here is my latest thinking on the likely pinout.


EDIT: outdated info removed. See msg #181 for the correct info.


Pins 20-31 are the "leftovers" which may be brought to bottom side pads, if space permits. They're in order of importance, so if space allows only 8, we'll get 20-27 and 28-31 will be left out. I'm also going to try cramming in (perhaps small) pads for access to the native SDIO and 2nd USB, so space will be tighter than Teensy 3.2. Odds seem slim we'll get all 12 leftover signals.

I've spent many long hours rearranging this list, especially with regard to how many of the UART RX/TX pairs to bring to the 24 outside pins. Several times I've considered 7 or even all 8 serial ports. As you can see on the list, I'm currently thinking of 5 serial ports on the outside pins. By giving up (placing on the leftover list) those last 3 serial ports, we get all the SAI/I2S digital audio pins, and much access the XBAR signals and FlexIO pins.

I also considered whether to put two full SPI ports on the outside pins. Still debating this. My current thinking is only full SPI on the outside, and access to a 2nd using bottom side plus pins 0 & 1. But we get lots of FlexIO pins, which can implement SPI (but not with the huge FIFO the normal SPI ports have). Another SPI decisions I've been struggling to make is regarding the hardware CS pins. On this new chip we don't get the same flexibility to do tricks like the ILI9341 library, so it's pretty likely we'll end up using FlexIO for optimized small TFT display libs.

[dukeblue219]

I would like to see a full port worth of pins available. 8 and/or 16 bits.

THIS.

Even if you can't write in an 8 or 16 bit mode and have to do some masking, I need the ability to write a whole port with a single GPIO register write (as in, a single bus cycle, so a custom function won't fly) if the 4.0 will replace my 3.2s and 3.6s at work. Realistically I want the Teensy 3.6 equivalent of this part if it comes, but for now, having a single parallel byte is important.

(If we can't work it out I'll still buy a couple to experiment with! Looking forward to this)

[KurtE]

What I see looks pretty good. I know there are many of us who what everything... But for example I have had few projects that really needed/used more than 3 USARTS of the T3.2, so having 5 is more than sufficient, especially if you have access through bottom pins for more.

I have found having a few SPI can be interesting, especially if you have DMA access to them and can have them doing things at same time... Two would be great, but if you can make up another SPI using the flex pins, my guess is that would work just fine in majority of cases. When you get closer to having beta boards I will want to rereview those sections. Wondering if these boards don't have SPI CS usage like the T3.2/5/6, where you can encode the CS and more importantly the DC pin on the queue, than wondering how often we would use hardware CS pin? Probably for slave? Wondering how much the FIFO helps the SPI speed? Obviously you want at least double buffering, and obviously a bit more is nice to reduce interrupts and latency...

I am assuming the IO pins are 3.3v only? I am also assuming that you can not aim for 100% drop in replacement for T3.2....
Otherwise you would have a few more IO pins (A10, 11...) My guess is the new chip(s) would not give you room for those 3 internal pins. And you already mentioned, that you did not have any signal pins on the far end pins...

Now back to playing!

But let me know if I can help

[Theremingenieur]

Apparently I’m suddenly old and need stronger reading glasses. Or can anyone confirm that there are no DAC pins? As someone working a lot in the mixed digital and analog domain, I thought that a more powerful processor than the T3.6 would not forcibly have more than the 2 ADCc and the 2 DACs, but also not less and hopefully higher speed and/or resolution...

[MichaelMeissner]

Apparently I’m suddenly old and need stronger reading glasses. Or can anyone confirm that there are no DAC pins? As someone working a lot in the mixed digital and analog domain, I thought that a more powerful processor than the T3.6 would not forcibly have more than the 2 ADCc and the 2 DACs, but also not less and hopefully higher speed and/or resolution...

According to page 212 it has:

Analog:

• 3x Analog-Digital-Converters (ADC), one of which supports differential inputs
• 2x Digital-Analog-Converters (DAC)
• 8x Analog Comparators (ACMP)

And also:

• SAI1–3 are synchronous serial interfaces used to transfer audio data. They can be accessed by both the eDMA and ARM CPUs. Their input/output are connected to the pads through IOMUX.
• MQS (medium quality speaker) is used to convert the I2S audio data from SAI to PWM signals that can drive external speaker directly. Its audio source comes from SAI-3 and its output is connected to pads through IOMUX.
• The SPDIF (Sony/Philips digital interface) audio module is a stereo transceiver that allows the processor to receive and transmit digital audio over it. The SPDIF receiver section includes a frequency measurement block that allows the precise measurement of an incoming sampling frequency. A recovered clock is provided by the SPDIF receiver section and may be used to drive both internal and external components in the system.

[WMXZ]

Obviously, I have as everyone added requirements to a new system, but It would be a big plus, if the T4.0 would be a drop in overdrive of the T3.2 both in RAM and in disk access. I cannot wait for its implementation.