defragster
Senior Member+
Yeah - with the T4 redefine to linker attribute the old - make it NULL on ARM's will show up. I must have missed it before so not a recent change.
#ifdef TEENSYDUINO
#define TFT_DC 10
#define TFT_CS 4
#define STMPE_CS 3
#define SD_CS 8
#endif
//Adafruit_ILI9341 tft = Adafruit_ILI9341(TFT_CS, TFT_DC);
Adafruit_ILI9341 tft = Adafruit_ILI9341(TFT_CS, TFT_DC, 11, 13, 1, 12);
#ifdef __AVR__
#include <avr/io.h>
#include <avr/pgmspace.h>
#elif defined(ESP8266)
#include <pgmspace.h>
#elif defined(TEENSYDUINO)
#include <avr/pgmspace.h>
#else
#define PROGMEM
#endif
#if defined(__AVR__) || defined(TEENSYDUINO)
#include <avr/io.h>
#include <avr/pgmspace.h>
#elif defined(ESP8266)
#include <pgmspace.h>
#else
#define PROGMEM
#endif
F:\arduino-1.8.8-t4\hardware\teensy\avr\cores\teensy3\Stream.cpp: In member function 'bool Stream::findUntil(const char*, const char*)':
EDIT2: The interesting thing is for the T3.x test compiles shows its happy with the original defines. Exception is I get this warning:
Code:F:\arduino-1.8.8-t4\hardware\teensy\avr\cores\teensy3\Stream.cpp: In member function 'bool Stream::findUntil(const char*, const char*)':
Would it possible for you to maintain a copy of GFX in your repositories?
Yes. In fact, one of the *many* things I want to do later this year or maybe in 2020 (everything takes longer than anticipated) is better display libs with a common API having more features.
...
View attachment 15819
Got this thing to play with when audio is working..
SCB_CCR 0x70200
SCB_ID_CCSIDR 0xF01FE019
SCB_ID_CSSELR 0x0
SCB_ID_CLIDR 0x9000003
N 1000 REPS 1000
memory addr us mflops sum
stack/DTCM 0x2001E088 11676 171.3 38217888
malloc/OCRAM 0x60002204 11733 170.5 38217888
PROGMEM/flash 0x20200008 11676 171.3 38217888
D cache off
stack/DTCM 0x2001E088 11676 171.3 38217888
malloc/OCRAM 0x60002204 1132899 1.8 38217888
PROGMEM/flash 0x20200008 80016 25.0 38217888
SCB_CCR 0x60200
D cache on 10000-element vectors, 100 reps, vectors bigger than 32KB Dcache
N 10000 REPS 100
memory addr us mflops sum
stack/DTCM 0x2000C748 11668 171.4 0
malloc/OCRAM 0x6000AEA4 213298 9.4 0
PROGMEM/flash 0x20200008 18950 105.5 0
Many SDK examples uses SCB_DisableDCache() or use memory sections marked as non-cacheable.
It doesn't appear that I can write to PROGMEM, is that correct?
SCB_MPU_RBAR = 0x60000000 | REGION(5); // QSPI Flash
SCB_MPU_RASR = MEM_CACHE_WBWA | READONLY | SIZE_16M;
why is OCRAM slower than PROGMEM?
Kurt,FYI - I just pushed up a different implementation of the SPIFlex(buf, retbuf, cnt), that may work differently. At least it is not hanging on my test program. ...
Edit2: Looks like I need to do a little more testing/updates, that is my dual display SSD1306 is hanging when I do the Flex display update along with the SPI doing Async update... Will try some more hacks here...
// err check jumper 2 to 3 MOSI to MISO
for (int i = 0; i < sizeof(txbuf); i++) txbuf[i] = i;
memset(rxbuf, 0, sizeof(rxbuf));
assert_cs();
SPIFLEX.transfer(txbuf, rxbuf, sizeof(txbuf));
release_cs();
Kurt,
my transfer(txbuf,rxbuf,cnt) isn't hanging any more. I still get lots of errors asking for 40mhz (with 160mhz flexio clock) and there is interframe gap. No gaps asking for 30mhz and ALMOST NO ERRORS. I'm actually getting one error on ALL transfers! txbuf[0] is being over-written ?????? I reset at the start of each iteration.
Code:// err check jumper 2 to 3 MOSI to MISO for (int i = 0; i < sizeof(txbuf); i++) txbuf[i] = i; memset(rxbuf, 0, sizeof(rxbuf)); assert_cs(); SPIFLEX.transfer(txbuf, rxbuf, sizeof(txbuf)); release_cs();
rxbuf sits in front of txbuf, so i'm assuming rxbuf is overflowing getting one more byte than it should.
there is debug led code in input i2s - please delete that before making a new installer
AttachInterrupt: Is :: memory sufficiant? I'd think a dmb or dsb may be needed, too.
We can move the vectortable to ITCM -manitou tested this and it was the same speed. This would free someRAM for variables/stack.
class SPISettings {
public:
SPISettings(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) :
[COLOR="#FF0000"] _clock(clock), _bitOrder(bitOrder), _dataMode(dataMode)[/COLOR]
{
if (__builtin_constant_p(clock)) {
init_AlwaysInline(clock, bitOrder, dataMode);
} else {
init_MightInline(clock, bitOrder, dataMode);
}
}
SPISettings() {
init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0);
}
[COLOR="#FF0000"]uint32_t inline clock() {return _clock;}
uint8_t inline bitOrder() {return _bitOrder;}
uint8_t inline dataMode() {return _dataMode;}[/COLOR]
private:
void init_MightInline(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) {
init_AlwaysInline(clock, bitOrder, dataMode);
}
void init_AlwaysInline(uint32_t clock, uint8_t bitOrder, uint8_t dataMode)
__attribute__((__always_inline__)) {
// TODO: Need to check timings as related to chip selects?
const uint32_t clk_sel[4] = {664615384, // PLL3 PFD1
720000000, // PLL3 PFD0
528000000, // PLL2
396000000}; // PLL2 PFD2
uint32_t cbcmr = CCM_CBCMR;
uint32_t clkhz = clk_sel[(cbcmr >> 4) & 0x03] / (((cbcmr >> 26 ) & 0x07 ) + 1); // LPSPI peripheral clock
uint32_t d, div;
if (clock == 0) clock =1;
d= clkhz/clock;
if (d && clkhz/d > clock) d++;
if (d > 257) d= 257; // max div
if (d > 2) {
div = d-2;
} else {
div =0;
}
ccr = LPSPI_CCR_SCKDIV(div) | LPSPI_CCR_DBT(div/2);
tcr = LPSPI_TCR_FRAMESZ(7); // TCR has polarity and bit order too
// handle LSB setup
if (bitOrder == LSBFIRST) tcr |= LPSPI_TCR_LSBF;
// Handle Data Mode
if (dataMode & 0x08) tcr |= LPSPI_TCR_CPOL;
// Note: On T3.2 when we set CPHA it also updated the timing. It moved the
// PCS to SCK Delay Prescaler into the After SCK Delay Prescaler
if (dataMode & 0x04) tcr |= LPSPI_TCR_CPHA;
}
uint32_t ccr; // clock config, pg 2660 (RT1050 ref, rev 2)
uint32_t tcr; // transmit command, pg 2664 (RT1050 ref, rev 2)
[COLOR="#FF0000"] uint32_t _clock;
uint8_t _bitOrder;
uint8_t _dataMode;[/COLOR]
friend class SPIClass;
};
AudioShield to T4 Connections
Do you have one of the breakout boards, with the switch for I2S1 vs I2S2?
If you remove the T4 and audio shield, and power it up with external 3.3V, you can check the signal paths with an ohm-meter. The switch controlls five 74LVC1G3157 analog switches, which should measure approx 6 ohms.
For I2S2, MCLK is pin 33 on the bottom side.
EDIT: for anyone who doesn't have the breakout board and wants try audio or USB host, email me directly. I have more parts coming Friday, so we should have 8 more of those available next week.
Sounds like I need to try out your version of test and see what is going on. Obviously the overwrite could be a bug... Will test again.
#include <FlexIO_t4.h>
#include <FlexSPI.h>
#define SPIHZ 30000000
//#define HARDWARE_CS
#ifdef HARDWARE_CS
FlexSPI SPIFLEX(2, 3, 4, 5); // Setup on (int mosiPin, int misoPin, int sckPin, int csPin=-1) :
#define assert_cs()
#define release_cs()
#else
FlexSPI SPIFLEX(2, 3, 4, -1); // Setup on (int mosiPin, int misoPin, int sckPin, int csPin=-1) :
#define assert_cs() digitalWriteFast(5, LOW)
#define release_cs() digitalWriteFast(5, HIGH)
#endif
void setup() {
pinMode(13, OUTPUT);
while (!Serial && millis() < 4000);
Serial.begin(115200);
delay(500);
#ifndef HARDWARE_CS
pinMode(5, OUTPUT);
release_cs();
#endif
SPIFLEX.begin();
// See if we can update the speed...
SPIFLEX.flexIOHandler()->setClockSettings(3, 2, 0); // clksel(0-3PLL4, Pll3 PFD2 PLL5, *PLL3_sw)
Serial.printf("Updated Flex IO speed: %u\n", SPIFLEX.flexIOHandler()->computeClockRate());
Serial.printf("SPIHZ %d\n", SPIHZ);
}
uint8_t txbuf[1024], rxbuf[1024];
void loop() {
SPIFLEX.beginTransaction(FlexSPISettings(SPIHZ, MSBFIRST, SPI_MODE0));
#if 1
assert_cs();
uint32_t t = micros();
SPIFLEX.transfer(txbuf, NULL, sizeof(txbuf));
t = micros() - t;
Serial.printf("%d us %.1f mbs\n", t, 8.*sizeof(txbuf) / t);
release_cs();
#endif
// err check jumper 2 to 3 MOSI to MISO
for (int i = 0; i < sizeof(txbuf); i++) txbuf[i] = i;
memset(rxbuf, 0, sizeof(rxbuf));
assert_cs();
SPIFLEX.transfer(txbuf, rxbuf, sizeof(txbuf));
release_cs();
SPIFLEX.endTransaction();
int errs = 0;
for (int i = 0; i < sizeof(txbuf); i++) if (txbuf[i] != rxbuf[i]) errs++;
Serial.printf("errs %d [3] %d\n", errs, rxbuf[3]);
if (errs) {
for (int i = 0; i <= 4; i++) Serial.printf("%d %d %d\n", i, txbuf[i], rxbuf[i]);
for (int i = 500; i <= 504; i++) Serial.printf("%d %d %d\n", i, txbuf[i], rxbuf[i]);
for (int i = 1020; i <= 1023; i++) Serial.printf("%d %d %d\n", i, txbuf[i], rxbuf[i]);
}
delay(500);
}
surprised it would be faster than the OCRAM....
… OCRAM slower than PROGMEM …
Dcache on
11676 us stack
11732 us malloc
11676 us progmem
D cache off
11676 us stack
1132899 us malloc
80016 us progmem