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Thread: Teensy 4.0 First Beta Test

  1. #3826
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    Quote Originally Posted by manitou View Post
    Well, the proof may be in the pudding -- since it doesn't want to count above 10mhz.

    So I changed the test sketch to not use the interval timer (spin on micros() for a second), and before init'ing GPT2 clock, changed source clock to 150mhz
    CCM_CSCMR1 &= ~CCM_CSCMR1_PERCLK_CLK_SEL; // turn off 24mhz mode
    and sketch counted properly for PWM running at 15 mhz (which wasn't working in 24mhz mode).
    Works @30mhz, and when i PWM @40mhz, it reports 37.5mhz (as expected, max is 150mhz/4) well, maybe, because max PWM rate is also only 37.5 mhz.

    modified sketch
    ……..
    @manitou
    Thanks for checking - funny that's not the way I was reading the RM but then again I only read it twice Ran some tests with various inputs:
    Code:
    @10Mhz ==> 10000010
    @15Mhz ==> 15000013-15000017
    @20Mhz ==> 18750017-18750021
    @25Mhz ==> 25000024-25000027
    @30Mhz ==> 30000027-30000033
    @35Mhz & @40Mhz ==> 37500033-37500041
    Interesting the bumped at 20Mhz..... So now guess to have to change freqcount library

  2. #3827
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    Quote Originally Posted by mjs513 View Post
    Interesting the bumped at 20Mhz..... So now guess to have to change freqcount library
    Well, that's discretization error from the PWM divisors (150/4=37.5, /5 =30, 25, 21.4, 18.75, ...)

  3. #3828
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    Quote Originally Posted by manitou View Post
    Well, that's discretization error from the PWM divisors (150/4=37.5, /5 =30, 25, 21.4, 18.75, ...)
    @manitou

    Good to know - keep learning something new everyday Anyway made the change to freqcount library - no longer uses a timer - just the 1 second reading got up to 30Mhz reliable output using analogwritefreq
    Code:
    Input	Output
    5000000	5000007
    10000000	10000014
    20000000	18750027
    25000000	25000681
    30000000	30000041

  4. #3829
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    Quote Originally Posted by mjs513 View Post
    @manitou
    Anyway made the change to freqcount library
    So your lib changes include changing the source clock of GPT to 150mhz? Will that be viable since the the source clock for PIT timer also changes, and things like interval timer will break? Also GPT and PIT will be affected by any change to the CPU clock speed. When clocked from 24mhz oscillator, those timers are not affected by changes to CPU clock.

    Recall all of the clock functions that the NXP SDK used to determine what that base clock frequency was for a given timer ...

  5. #3830
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    Quote Originally Posted by manitou View Post
    So your lib changes include changing the source clock of GPT to 150mhz? Will that be viable since the the source clock for PIT timer also changes, and things like interval timer will break? Also GPT and PIT will be affected by any change to the CPU clock speed. When clocked from 24mhz oscillator, those timers are not affected by changes to CPU clock.

    Recall all of the clock functions that the NXP SDK used to determine what that base clock frequency was for a given timer ...
    Yeah - unfortunately know no other way around it unless we limit freqcount to 10Mhz but then again .. What do you recommend - keep it the way we have it or to change it - my guess is you are going to tell me to leave it limited to 10Mhz

    EDIT: Yeah - you are right - would cause too many other issues so let it be with just a note that there is a limit, https://github.com/PaulStoffregen/FreqCount/pull/11

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