It look like the SCB _ACTRL register is missing in the kinetic.h
Maybe not the most important one, but it should be there.

#define SCB_ACTRL (*(volatile uint32_t *)0xE000E008) // Auxiliary control register

Bits 31:10 Reserved

Bit 9          DISOOFP  
                 Disables floating point instructions completing out of order with respect to integer instructions.

Bit 8          DISFPCA 
                 Disables automatic update of CONTROL.FPCA.
                 The value of this bit should be written as zero or preserved (SBZP).

Bit 7:3       Reserved

Bit 2          DISFOLD
                 Disables folding of IT instructions:
                 0: Enables IT instructions folding.
                 1: Disables IT instructions folding.
                 In some situations, the processor can start executing the first instruction in an IT block while it
                 is still executing the IT instruction. This behavior is called IT folding, and improves
                 performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the
                DISFOLD bit to 1 before executing the task, to disable IT folding.

Bit 1         DISDEFWBUF
                This bit only affects write buffers implemented in the Cortex-M4 processor.
                Disables write buffer use during default memory map accesses: This causes all BusFaults to
                be precise BusFaults but decreases performance because any store to memory must
                complete before the processor can execute the next instruction.
                0: Enable write buffer use
                1: Disable write buffer use: Stores to memory is completed before next instruction.

Bit 0         DISMCYCINT
                Disables interrupt of multi-cycle instructions. When set to 1, disables interruption of load
                multiple and store multiple instructions. This increases the interrupt latency of the processor
                because any LDM or STM must complete before the processor can stack the current state and
                enter the interrupt handler.
                0: Enable interruption latency of the processor (load/store and multiply/divide operations).
                1: Disable interruptions latency.