Forum Rule: Always post complete source code & details to reproduce any issue!
Results 1 to 5 of 5

Thread: Digital Delay Line

  1. #1

    Digital Delay Line

    I am new to the Teensy and am building a digital delay line for a continuous stream of 8-bit digital data @ 20MSa/s. I have designed it thus:

    1. Capture 8-bit data from an externally clocked ADC, that will give 20 MSa/sec and provide a 20 MHz interrupt for 2 x T3.6 overclocked to 240 MHz
    2. Write the ADC data to a Cypress dual ported SRAM, into a 16kB circular buffer using T3.6 No.1
    3. Time out for the delay period, min 350us, max 450us of T3.6 No. 1.
    4. Raise an interrupt on a GPIO pin of T3.6 No. 1
    5. Get T3.6 No. 2 to service the interrupt and begin reading the data in the dual ported RAM and write it to an R2R DAC @ 20 MHz
    6. After the first interrupt, both processors read and write synchronously using the external ADC clock as interrupt, thereby realizing a delay line.

    Is there a more efficient way of doing this?

  2. #2
    Senior Member+ Frank B's Avatar
    Join Date
    Apr 2014
    Location
    Germany NRW
    Posts
    5,588
    Quote Originally Posted by rajiv.tctech View Post
    I am new to the Teensy and am building a digital delay line for a continuous stream of 8-bit digital data @ 20MSa/s. I have designed it thus:

    1. Capture 8-bit data from an externally clocked ADC, that will give 20 MSa/sec and provide a 20 MHz interrupt for 2 x T3.6 overclocked to 240 MHz
    2. Write the ADC data to a Cypress dual ported SRAM, into a 16kB circular buffer using T3.6 No.1
    3. Time out for the delay period, min 350us, max 450us of T3.6 No. 1.
    4. Raise an interrupt on a GPIO pin of T3.6 No. 1
    5. Get T3.6 No. 2 to service the interrupt and begin reading the data in the dual ported RAM and write it to an R2R DAC @ 20 MHz
    6. After the first interrupt, both processors read and write synchronously using the external ADC clock as interrupt, thereby realizing a delay line.

    Is there a more efficient way of doing this?
    I doubt that this will work.
    240/20 = 12. You have 12 cpu-cycles to do that. Not counting the F_BUS, which is much lower clocked,and needed for I/O. You need an FPGA.

  3. #3
    Except for the speed problem, why not using 1 T3.6 and doing the delay line in the Teensy's RAM. That seems a lot easier to me and probably just as fast.

  4. #4
    Senior Member PaulStoffregen's Avatar
    Join Date
    Nov 2012
    Posts
    20,069
    Agreed, at this speed, this is a job for a FPGA.

  5. #5
    Thank you all for the advice... 🙏

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •