rajiv.tctech
Member
I am new to the Teensy and am building a digital delay line for a continuous stream of 8-bit digital data @ 20MSa/s. I have designed it thus:
1. Capture 8-bit data from an externally clocked ADC, that will give 20 MSa/sec and provide a 20 MHz interrupt for 2 x T3.6 overclocked to 240 MHz
2. Write the ADC data to a Cypress dual ported SRAM, into a 16kB circular buffer using T3.6 No.1
3. Time out for the delay period, min 350us, max 450us of T3.6 No. 1.
4. Raise an interrupt on a GPIO pin of T3.6 No. 1
5. Get T3.6 No. 2 to service the interrupt and begin reading the data in the dual ported RAM and write it to an R2R DAC @ 20 MHz
6. After the first interrupt, both processors read and write synchronously using the external ADC clock as interrupt, thereby realizing a delay line.
Is there a more efficient way of doing this?
1. Capture 8-bit data from an externally clocked ADC, that will give 20 MSa/sec and provide a 20 MHz interrupt for 2 x T3.6 overclocked to 240 MHz
2. Write the ADC data to a Cypress dual ported SRAM, into a 16kB circular buffer using T3.6 No.1
3. Time out for the delay period, min 350us, max 450us of T3.6 No. 1.
4. Raise an interrupt on a GPIO pin of T3.6 No. 1
5. Get T3.6 No. 2 to service the interrupt and begin reading the data in the dual ported RAM and write it to an R2R DAC @ 20 MHz
6. After the first interrupt, both processors read and write synchronously using the external ADC clock as interrupt, thereby realizing a delay line.
Is there a more efficient way of doing this?