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Thread: Change SampleRate

  1. #1

    Change SampleRate

    I have a setup consisting of the DACs as source. These deliver their data via a recordQueue to my program. My program does some filtering and puts the output data to playQueues. The data then goes to the DACs. So there is no SGTL5000 involved. Is it possible to change the samplerate?

  2. #2
    Senior Member+ Theremingenieur's Avatar
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    It is (within several limits, for example no USB audio). Several discussions about this topic exist already in these forums. Please do a search.

    A starting point could be utility/pdb.h where you might modify PDB_PERIOD which has an effect onto ADCs and DACs.

  3. #3
    So far I found that I had to change the constant 1360 in pdb.h

    Code:
    #elif F_BUS == 60000000
      #define PDB_PERIOD (1360-1)
    I could make the ADC clock a little slower, but not faster ( I want to go from 44100 to 96000 Samples / sec) . Probably something in the ADC/DAC setup has to be changed?

  4. #4
    Senior Member DD4WH's Avatar
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    hi Martin, what Thierry probably meant was this method by Frank B:

    https://forum.pjrc.com/threads/38753...ge+sample+rate

    Discussions on changing sample rate can also be found here:

    https://forum.pjrc.com/threads/53709...ge+sample+rate

    https://forum.pjrc.com/threads/38988...ge+sample+rate

    Good luck!

    Frank DD4WH

  5. #5
    The Method to change the I2S clock only works for the SGTL5000 as far as I see. The DAC and ADC timing is specified by the parameter PDB_PERIOD from pdb.h. Changing this from 1360 to 3000 makes the Sample rate 60MHz/3000=20000 samples/sec. That runs perfectly. But changing this parameter to 1000 makes the software stuck. Probably some other parameter must be changed also.

  6. #6
    Senior Member+ Frank B's Avatar
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    Quote Originally Posted by ossi View Post
    The Method to change the I2S clock only works for the SGTL5000 as far as I see. The DAC and ADC timing is specified by the parameter PDB_PERIOD from pdb.h. Changing this from 1360 to 3000 makes the Sample rate 60MHz/3000=20000 samples/sec. That runs perfectly. But changing this parameter to 1000 makes the software stuck. Probably some other parameter must be changed also.
    Hm the only other timing dependend stuff seems to bis this: https://github.com/PaulStoffregen/Au...t_adcs.cpp#L62
    Maybe try to reduce the analogReadAveraging(x)? (have not tried this)
    If this does not help, there must be an other issue.. I hope we can find it

  7. #7
    Quote Originally Posted by [URL
    https://github.com/PaulStoffregen/Audio/blob/828ea4a74c3b4db06261a4598fa6bb1bcf4f9787/input_adcs.cpp#L62[/URL]
    In input_adcs.cpp I see where the trigger rate of the ADCs is set to 44100 but I can not see where the ADC conversion clock is specified.
    Playing with analogReadAveraging(x) had no positive effect.

  8. #8
    Senior Member+ Frank B's Avatar
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    ok, take a look at analog.c in the core.

  9. #9
    It seems changing the CFG1 setting in analog.c and pdb_period in pdb.h does the trick.
    Thanks.

  10. #10

    summary?

    Quote Originally Posted by ossi View Post
    It seems changing the CFG1 setting in analog.c and pdb_period in pdb.h does the trick.
    Thanks.
    Can you please summarize how you have accomplished changing the sampling rate?

    Thanks much!

  11. #11
    in analog.c i made tzhe following change:
    Code:
    //#elif F_BUS == 60000000
    //  #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7.5 MHz
    //  #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
    //  #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
    //  #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
    #elif F_BUS == 60000000
      #define ADC_CFG1_16BIT  ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
      #define ADC_CFG1_12BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 30 MHz
      #define ADC_CFG1_10BIT  ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 30 MHz
      #define ADC_CFG1_8BIT   ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 30 MHz
    in pdb.h i made the following change:
    Code:
    #elif F_BUS == 60000000
      #define PDB_PERIOD (600-1)
    //  #elif F_BUS == 60000000
    //  #define PDB_PERIOD (1360-1)
    This changes the sampling rate to 60MHz/600=100kSamples/sec for the DACs and ADCs.

  12. #12
    Thank you!!!

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