I'm generating a PWM clock that varies between 1mhz to 191khz according to a midi cc controller. Ive been reading up on duty-cycles in variable pwm situations and have tried to design this in respect to the f_bus (60mhz t3.6), my understanding is that even divisions of f_bus allow pwm to stay at 50% duty?

What I've done is filled a 127 slot array with even divisions of 60,000,000 (60, 62, 64, 66, etc)

void setup() {


  for (byte i = 0; i < 128; i++) {
    double divider = (i * 2) + 60;
    clock_Array [i] = 60000000 / divider;
I've verified reading out the array after to serial that it is filling to with the right values, i.e;

16:49:38.783 -> 1000000.0000000000
16:49:38.783 -> 967741.9354838709
16:49:38.783 -> 937500.0000000000
16:49:38.783 -> 909090.9090909090
16:49:38.783 -> 882352.9411764706
16:49:38.783 -> 857142.8571428571
16:49:38.783 -> 833333.3333333333

The issue is that I am not measuring 50% duty cycle near the high end of the clock, the duty reads duty+ 46.9%, duty - 53.1%. As i slow down the pwm clock the duty gets closer to 50/50, but not at the high end. Also, is this normal for a pwm out signal @ 1mhz, was hoping for something more clean. See;


Everything is going well for the most part, but i am getting some glitches in the instrument I'm controlling, sometimes it crashes. Trying to rule out duty issues.

the code i'm using to write on midi cc changes is simply;

analogWrite(PWMpin1, 0);
analogWriteFrequency(PWMpin1, clock_Array[value]); //
analogWrite(PWMpin1, 127);
Any ideas about the irregular duty cycle at 1mhz end of the scale?

Thanks in advance