With T4 - only Pin 10 is CS pin on that SPI buss - And it works very differently than T3.x

That is with T4 you con't have the PUSHR register where you can select which if any (may be more than one) are to be asserted during that SPI transfer, and the CONT bit will say if those assertions should continue after that transfer completes.

Instead with the T4 you do have a FIFO queue, and you have two different registers that can be put onto the queues:
The standard: TDR which you can transfer up to 32 bits of data
And the TCR (Transfer control register) which you can adjust things like word size... With this you can choose which CS channel to assert (only one), and the T4 only has one that was routed out to external IO pin... So very different. With T4 in for example my ili9341_t3n library I got a very slight speedup by using DC on pin 10... But just slight.