PT8211 and teensy 3.6 240 mhz overclock

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Frassil

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Hi!

I'm wondering if PT8211 and teensy 3.6 240 mhz overclock works nicely together?
Or is it like the Audio board, where more than 192mhz is trouble?
 
The Teensy is the problem, not the Audio Shield. The 3.6's I2S device does not like the overclocking and has hefty problems creating the cock signals > 192MHz.
So, I don't think that it works better with the PT8211.
 
Okey, did order some anyway for testing.

BTW!
Got it working really nice at 240mhz and an UDA1334A board (this board doesnt need the MLCK) . I also needed to change the fractional dividers in output_i2s.cpp to:
#elif F_CPU == 240000000
#define MCLK_MULT 2 //4 default in audio lib
#define MCLK_DIV 85 //85 default in audio lib
#define MCLK_SRC 0 //not defined in audio lib

as stated by neurofun in the end of this thread:
https://forum.pjrc.com/threads/4803...40MHz-and-audio-adapter-board-gt-LRCLK-jitter

I have an audio board and will test it as well in a few days.
If this works with audio board, maybe audio lib need an update on this?

I'm so happy i now can upgrade my "forever project" Elektroraum
It got 3x Teensy 3.6@240mhz running with built in dac as output, summed together and trough 6-order lowpass, Resolution is ok for me i think with 12bit, but it's so noisy.
But now i can upgrade to I2S and get much cleaner sound :) :)

Here it is (can't upload pic :/)!
https://ibb.co/zbGHT50
 
The Teensy is the problem, not the Audio Shield. The 3.6's I2S device does not like the overclocking and has hefty problems creating the cock signals > 192MHz.
So, I don't think that it works better with the PT8211.
@Frank B: It looks to like most of the I2S fractional clock dividing in the audio lib is done based on F_CPU/F_PLL. Selecting F_BUS as the clock source and adapting the fractional divider defines in the audio lib could probably solve these overclocking problems...
 
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