That's a really clear bit of documentation. Well done. Can I ask how you made it?
Yep it is a nice set of cards!
Just an FYI, for other forms of the data:
There is a table of all of the pins in the Beta thread:
https://forum.pjrc.com/threads/54711-Teensy-4-0-First-Beta-Test?p=193716&viewfull=1#post193716
I have most of the same data in my Excel spreadsheet I made during the T4 beta, now up on github:
https://github.com/KurtE/TeensyDocuments/blob/master/Teensy4 Pins.xlsx
During each of the recent betas, several of us have generated these tables from the information Paul put into the first beta builds, plus the reference manuals.
For example if you look at the file cores\teensy4\core_pins.h
You will find a whole lot of defines sort of in different tables...
Example sections like:
Code:
#define CORE_PIN0_BIT 3
#define CORE_PIN1_BIT 2
#define CORE_PIN2_BIT 4
#define CORE_PIN3_BIT 5
#define CORE_PIN4_BIT 6
#define CORE_PIN5_BIT 8
...
And
Code:
#define CORE_PIN0_PORTREG GPIO6_DR
#define CORE_PIN1_PORTREG GPIO6_DR
#define CORE_PIN2_PORTREG GPIO9_DR
#define CORE_PIN3_PORTREG GPIO9_DR
#define CORE_PIN4_PORTREG GPIO9_DR
#define CORE_PIN5_PORTREG GPIO9_DR
So we know that the first few pins are: 6:3, 6:2, 9:4, 9:5, 9:6, 9:8
Which side not show up as 1.3 1.2 4.4... in my table as this was done before mapping to faster ports (also was done originally during beta 1 with 1052).
And a Bigger Hint is the set of defines for the PAD control:
Code:
#define CORE_PIN0_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
#define CORE_PIN1_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
#define CORE_PIN2_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
#define CORE_PIN3_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
#define CORE_PIN4_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
#define CORE_PIN5_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
#define CORE_PIN6_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
#define CORE_PIN7_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
#define CORE_PIN8_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
#define CORE_PIN9_CONFIG IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
This is actually showing the real underlying pins: GPIO_AD_B0_03, GPIO_AD_B0_02, ...
Now from this you can find a lot/most of the data associated with the pins in the IMXRT1060RM document probably the smaller document as well. But if you look starting in chapter 7 for the string GPIO_AD_B0_03 You will run into several places this pin can be configured. And you can find it a few different ways.
You will run into Table 9-1 muxing options like on P297 you find that it can be FLEXPWM1_PWM1_X when configured to ALT4, and FlexCan... GPIO1 (ALT5)
But the best place to find this pin is in section 10.7.46:
(IOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
Which shows all of the MUX modes for this pin:
Code:
MUX_MODE MUX Mode Select Field.
Select one of iomux modes to be used for pad: GPIO_AD_B0_03.
000 ALT0 — Select mux mode: ALT0 mux port: FLEXCAN2_RX of instance: flexcan2
001 ALT1 — Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1
010 ALT2 — Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6
011 ALT3 — Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: usb
100 ALT4 — Select mux mode: ALT4 mux port: FLEXPWM1_PWMX01 of instance: flexpwm1
101 ALT5 — Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1
110 ALT6 — Select mux mode: ALT6 mux port: REF_CLK_24M of instance: anatop
111 ALT7 — Select mux mode: ALT7 mux port: LPSPI3_PCS0 of instance: lpspi3
Now all you have to do is to repeat for each of the IO pins...