Teensy 4 FTM input capature capabilities

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u_cap

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Teensy 4 FlexTimer Module (FTM) / Quad Timer (QTIMER) Input Capture capabilities

Just in case somebody has already dug out relevant specs:

I am using Teensy 3.x for FTM input capture, targeting bursts of pulses at modulation frequencies between 1.8MHz and 10MHz, with burst O(10-100) pulses repeated at varying intervals with an average repeat rate of 120 bursts/sec to 400 bursts/sec. There are multiple of these inputs, I am handling up to 8 of these on a Teensy 3.x.

There are two different modulation types I need to handle:

* One is constant carrier frequency per burst, but could vary from one burst to the next.
* The other is an LFSR / Manchester modulation, e.g. a 3/6 MHz FSK

https://github.com/cnlohr/esptracker/issues/1#issuecomment-410804130

What I ultimately need is an MCU capturing 20+ inputs, with 48/60/more MHz FTM, distinguishing rising and failing edge of each modulation pulse.

What FTM sampling frequency does Teensy4 support?
How many concurrent FTM inputs can it service?
Can it distinguish rising and falling on a single input?

What kind of CPU load as a function of N_inputs * N_pulses/burst * N_avg_bursts/second ?

Thanks!
 
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From the various beta threads:

* https://github.com/PaulStoffregen/FreqCount T4 updates
* https://github.com/manitou48/teensy4 qtmr_ experiment sketches

I lost track on pinout revisions, but at one point:

Code:
10   B0_00      QT1_0
11   B0_02      QT1_2
12   B0_01      QT1_1
13   B0_03      QT2_0  
     AD_B1_02   QT3_2
     AD_B1_03   QT3_3
18   AD_B1_01   QT3_1 
19   AD_B1_00   QT3_0

It looks like QTIMER#x_TIMER#y with x=[1-4], y=[0-3] means the chip has 16, but only 6 are exposed by pin and 8 are connected on T4?

From:
https://forum.pjrc.com/threads/52761-Teensy-4-0-(hypothetical)-pin-assignments
 
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Only pinout overview I found calling out Quad Timers:

https://forum.pjrc.com/attachment.php?attachmentid=15040&d=1540676635

Implies 9 concurrent inputs.

Ignore that pinout. That was made based on first discussions about what the POTENTIAL PINOUT could look like. I know because I made it. The latest and most accurate is in post #6 of the T4 beta thread.

Based on testing of the FreqCount library looks like it will work up 65Mhz with no issue. Thanks to @manitou for putting that together.
 
Only pinout overview I found calling out Quad Timers:

https://forum.pjrc.com/attachment.php?attachmentid=15040&d=1540676635

Implies 9 concurrent inputs.

look at the table in https://forum.pjrc.com/threads/54711-Teensy-4-0-First-Beta-Test?p=193716&viewfull=1#post193716
There is a PWM column. Entries like QTx_n are QuadTimer PWM, others are eFlexPWM. a couple of PWM pins can be configured for either timer.

chapter 9 of T4 ref manual has tables mapping peripherals/timers to pins.
 
The latest and most accurate is in post #6 of the T4 beta thread.

The card does not list QTM, is Beta2 identical to final T4?

Code:
10     B0_00      2.0                  4:CS0   QT1_0          MQS_RIGHT          2:0     
11     B0_02      2.2                  4:MOSI  QT1_2    1_TX                     2:2
12     B0_01      2.1                  4:MISO  QT1_1          MQS_LEFT           2:1     
13     B0_03      2.3                  4:SCK   QT2_0    1_RX                     2:3
14/A0  AD_B1_02   1.18  UART2_TX               QT3_2          SPDIF_OUT          3:2     A1:7,A2:7
15/A1  AD_B1_03   1.19  UART2_RX               QT3_3          SPDIF_IN           3:3     A1:8,A2:8
16/A2  AD_B1_07   1.23  UART3_RX  3_SCL                       SPDIF_EXTCLK       3:7     A1:12,A2:12
17/A3  AD_B1_06   1.22  UART3_TX  3_SDA                       SPDIF_LOCK         3:6     A1:11,A2:11
18/A4  AD_B1_01   1.17   2_cts    1_SDA        QT3_1                             3:1     A1:6,A2:6
19/A5  AD_B1_00   1.16            1_SCL        QT3_0                             3:0     A1:5,A2:5
20/A6  AD_B1_10   1.26  UART8_TX                              1:RX_SYNC          3:10    A1:15,A2:15

11 concurrent channels at 65MHz, up from 8 at 60MHz for Teensy 3.5/6?

Are these capable of distinguishing rising from falling on dual-edge input capture?
 
Entries like QTx_n are QuadTimer PWM, others are eFlexPWM. a couple of PWM pins can be configured for either timer.

Would it be possible to do PulsePosition input capture on eFlexPWM as well?

chapter 9 of T4 ref manual has tables mapping peripherals/timers to pins.

You mean the NXP reference manual (non-login version) ?

https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf

I see Chapter 9 able 9-1 shows TMR1-4 with 4 channels each, so in theory a large PCB Teensy 4.x could offer up to 16 of these?

Chapter 52 Quad Timer (TMR), and 53 for the flex PWM - thanks, I'll have some reading.
 
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