Teensy 4.0 on high speed parallel bus?

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Macona

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So I need to make a usb interface for a serial communications setup we use here at work. It send 7 bits parallel at 50Mhz into a LVDS transmitter (SN65LVDS95DGG) and also receives the same on a 50Mhz clock. I realize that's potentially a lot of data but I really only need this to transmit commands and receive the results from those commands.

Any idea if the 4.0 will be fast enough to do this, basically I am trying to avoid spending lots of money off a FPGA board.
 
I don't know enough to say but just as a guess, if this is full-duplex, eg sending 7 bits and receiving 7 bits at the same time, I suspect the FPGA is a safer bet at this point. Maybe even if it's half-duplex. It may be that the i.MX RT1060 chip itself is capable enough, but AFAIK the Teensy 4 implementation was not designed for this use.

You can find the T4 schematic here: https://www.pjrc.com/teensy/schematic.html
The pins available were chosen to enable the most different functions while making it mostly compatible with earlier Teensy boards, and not with parallel bus needs in mind.
 
I think the most adjacent parallel bits on any one port is six with this Teensy. You'll have to do some rearranging of your commands to send 7 or eight bit words, though it sounds like that should be doable for what your have in mind. The Teensy can also do parallel GPIO operations near thst speed but it's never going to be exactly 50 MHZ. If your sending clocks can vary thst may also work, but I think receiving a 50 MHZ synchronous clocked bus will be really tough. You're already going to be working with just a couple clock cycles per word received so trying to sync up with a clocked IO is going to be a challenge.

I don't know what your fpga skills are like but there are cheap FPGA boards out there. You don't need much to drive your parallel bus at 50 MHZ and detect a specific pattern to drive an IO line upon receipt of a particular command.
 
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