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Thread: Teensy 4.0 I2S crackling noise

  1. #1
    Senior Member DD4WH's Avatar
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    Teensy 4.0 I2S crackling noise

    I have been trying to use the Teensy 4.0 with the PJCR Teensy Audio shield to get I2S audio input and output.

    The audio shield was soldered with very short wires (< 2cm) and 100 Ohms series resistor in MCLK. photo can be seen here:

    https://forum.pjrc.com/threads/57167...l=1#post214168

    All works fine, but there is a horrible crackling noise in the audio.

    Then I tried the Teensy 4.0 with the ADC PCM1808 and the DAC PCM5102A (with long wires!) -> that worked, but there is also that horrible crackling noise.

    When I lower the sample rate (with the code by FrankB), however, the noise disappears. With 24ksps or lower, I am safe from all the noise [EDIT: it seems this is not entirely true, the noise is not permanent, but now and then it will crack].

    I tried the very same setup with a Teensy 3.6 with the ADC PCM1808 and the DAC PCM5102A (with the same long wires!). All is perfectly fine up to 234ksps (overclocking the ADC and DAC heavily) with fine audio. No crackling noise at all.

    Then I tried these lines in the Teensy 4.0 setup to lower the drive strength of MCLK, suggested by Blackaddr:

    Code:
    // defaults were all 0x10B0 which is keeper, Medium speed (100 Mhz), drive strength = R0/6 = 150/6 = 25 ohms (the second strongest drive strength available)
    // My changes were:
    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 0xF808; // SCL, pullup at 22K, open drain enable, low speed, drive strength at R0 (150 ohm)
    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 0xF808; // SDA
    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 0x8; // MCLK, low speed, drive strength at R0 (150 ohm).
    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 0x8; // BCLK
    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 0x8; // LRCLK
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 0x8; // OUT1A
    Again, there is no difference in behaviour when I insert those lines into the setup of my sketch.

    It seems to me that there is still something fundamentally wrong in the way I use external I2S ADC/DAC with the Teensy 4.0.

    What is different in the way the Teensy 4.0 handles I2S compared to the Teensy 3.6? The latter works perfectly with exactly the same setup/wires etc. . . .

    I would be grateful if anybody could point me in the right direction in order to get reliable audio function with the Teensy 4.0.

    All the best,

    Frank DD4WH

    MCLK = 23
    BCLK = 21
    LRCLK = 20
    TX = 7
    RX = 8
    GND = GND
    3V3 = 3V3
    Vin = 5V

  2. #2
    Quote Originally Posted by DD4WH View Post
    I have been trying to use the Teensy 4.0 with the PJCR Teensy Audio shield to get I2S audio input and output.

    The audio shield was soldered with very short wires (< 2cm) and 100 Ohms series resistor in MCLK. photo can be seen here:

    https://forum.pjrc.com/threads/57167...l=1#post214168

    All works fine, but there is a horrible crackling noise in the audio.

    Then I tried the Teensy 4.0 with the ADC PCM1808 and the DAC PCM5102A (with long wires!) -> that worked, but there is also that horrible crackling noise.

    When I lower the sample rate (with the code by FrankB), however, the noise disappears. With 24ksps or lower, I am safe from all the noise [EDIT: it seems this is not entirely true, the noise is not permanent, but now and then it will crack].

    I tried the very same setup with a Teensy 3.6 with the ADC PCM1808 and the DAC PCM5102A (with the same long wires!). All is perfectly fine up to 234ksps (overclocking the ADC and DAC heavily) with fine audio. No crackling noise at all.

    Then I tried these lines in the Teensy 4.0 setup to lower the drive strength of MCLK, suggested by Blackaddr:

    Code:
    // defaults were all 0x10B0 which is keeper, Medium speed (100 Mhz), drive strength = R0/6 = 150/6 = 25 ohms (the second strongest drive strength available)
    // My changes were:
    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 0xF808; // SCL, pullup at 22K, open drain enable, low speed, drive strength at R0 (150 ohm)
    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 0xF808; // SDA
    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 0x8; // MCLK, low speed, drive strength at R0 (150 ohm).
    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 0x8; // BCLK
    IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 0x8; // LRCLK
    IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 0x8; // OUT1A
    Again, there is no difference in behaviour when I insert those lines into the setup of my sketch.

    It seems to me that there is still something fundamentally wrong in the way I use external I2S ADC/DAC with the Teensy 4.0.

    What is different in the way the Teensy 4.0 handles I2S compared to the Teensy 3.6? The latter works perfectly with exactly the same setup/wires etc. . . .

    I would be grateful if anybody could point me in the right direction in order to get reliable audio function with the Teensy 4.0.

    All the best,

    Frank DD4WH

    MCLK = 23
    BCLK = 21
    LRCLK = 20
    TX = 7
    RX = 8
    GND = GND
    3V3 = 3V3
    Vin = 5V
    :-)
    really ?

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