FreqMeasure capabilities on T3.6 and T4

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dauntless89

Well-known member
Hello,

I am potentially going to be measuring a square-wave signal (.5 to 5KHz) with a Teensy 3.6 and possibly later a Teensy 4.

The low end of this range is a major control input for my project, as such I would prefer to use FreqMeasure to have the best resolution possible below 1KHz. The signal will also have control implications at the high end of the range as well, but actualization requirements up there aren't nearly so stringent.

It doesn't seem like the reference pages have been updated recently, perhaps not significantly since the release of T3.1, and I wanted to clarify the theoretical limits of the FreqMeasure library on the newest Teensy models. The reference page states:

At higher frequencies, the short time can only be measured at the processor's clock speed, which results in limited resolution.

Can this be interpreted to mean that a T3.6 at factory clock speeds running FreqMeasure can theoretically read 180MHz? Or perhaps it would be an octave of this clock speed. Anyway, any input on this point would be appreciated.
 
You can see the F_BUS defines for teensy 3.x in kinetis.h file here: on MS WIN10 - Drive C:\Users\***\**\arduino-1.8.9\hardware\teensy\avr\cores\teensy3\kinetis.h

Code:
#if (F_CPU == 256000000)
 #define F_PLL 256000000
 #ifndef F_BUS
 #define F_BUS 64000000
 //#define F_BUS 128000000  // all the usual overclocking caveats apply...
 #endif
 #define F_MEM 32000000
#elif (F_CPU == 240000000)
 #define F_PLL 240000000
 #ifndef F_BUS
 #define F_BUS 60000000
 //#define F_BUS 80000000   // uncomment these to try peripheral overclocking
 //#define F_BUS 120000000  // all the usual overclocking caveats apply...
 #endif
 #define F_MEM 30000000
#elif (F_CPU == 216000000)
 #define F_PLL 216000000
 #ifndef F_BUS
 #define F_BUS 54000000
 //#define F_BUS 72000000
 //#define F_BUS 108000000
 #endif
 #define F_MEM 27000000
#elif (F_CPU == 192000000)
 #define F_PLL 192000000
 #ifndef F_BUS
 #define F_BUS 48000000
 //#define F_BUS 64000000
 //#define F_BUS 96000000
 #endif
 #define F_MEM 27428571
#elif (F_CPU == 180000000)
 #define F_PLL 180000000
 #ifndef F_BUS
 #define F_BUS 60000000
 //#define F_BUS 90000000
 #endif
 #define F_MEM 25714286
#elif (F_CPU == 168000000)
 #define F_PLL 168000000
 #define F_BUS 56000000
 #define F_MEM 28000000
#elif (F_CPU == 144000000)
 #define F_PLL 144000000
 #ifndef F_BUS
 #define F_BUS 48000000
 //#define F_BUS 72000000
 #endif
 #define F_MEM 28800000
#elif (F_CPU == 120000000)
 #define F_PLL 120000000
 #ifndef F_BUS
 #define F_BUS 60000000
 //#define F_BUS 120000000
 #endif
 #define F_MEM 24000000
#elif (F_CPU == 96000000)
 #define F_PLL 96000000
 #ifndef F_BUS
 #define F_BUS 48000000
 //#define F_BUS 96000000
 #endif
 #define F_MEM 24000000
#elif (F_CPU == 72000000)
 #define F_PLL 72000000
 #ifndef F_BUS
 #define F_BUS 36000000
 //#define F_BUS 72000000
 #endif
 #define F_MEM 24000000
#elif (F_CPU == 48000000)
 #define F_PLL 96000000
 #if defined(KINETISK)
 #define F_BUS 48000000
 #elif defined(KINETISL)
 #define F_BUS 24000000
 #endif
 #define F_MEM 24000000
#elif (F_CPU == 24000000)
 #define F_PLL 96000000
 #define F_BUS 24000000
 #define F_MEM 24000000
#elif (F_CPU == 16000000)
 #define F_PLL 16000000
 #define F_BUS 16000000
 #define F_MEM 16000000
#elif (F_CPU == 8000000)
 #define F_PLL 8000000
 #define F_BUS 8000000
 #define F_MEM 8000000
#elif (F_CPU == 4000000)
 #define F_PLL 4000000
 #define F_BUS 4000000
 #define F_MEM 4000000
#elif (F_CPU == 2000000)
 #define F_PLL 2000000
 #define F_BUS 2000000
 #define F_MEM 1000000
#endif
 
That's funny, when I first read that paragraph in the reference article, I thought "I bet 'processor' clock really means 'F_BUS' clock." Thanks for confirming.

I guess I find it a little odd that the recommended frequency limit is so low (1KHz) in the reference article, but I guess I just need to experiment to see if a 5KHz signal clogs up the tubes too much. I will also take the divisor into account if I play with overclocking it.
 
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