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Thread: Teensy 4 - SPI bus > 38mhz possible?

  1. #1
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    Teensy 4 - SPI bus > 38mhz possible?

    It looks like 38mhz is what the spi bus tops out at on T4, is it possible to go higher? I saw other posts talking about T3 F_BUS /2 = SPI clock, is it the same in T4?

    edit: looks like it is f_bus /2 = max spi clock so can you increase the f_bus w/o overclocking the cpu or is that the only way?
    Last edited by 1of9; 09-18-2019 at 11:10 AM.

  2. #2
    Senior Member+ KurtE's Avatar
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    It is a little more complicated than that...

    The SPI buss speed can be based off of 4 different clocks and have an initial divider set. This part is controlled by the CBCMR register.
    Not sure if I am looking at the same version of the reference manual that is up on PJRC, but the CCM clock tree is shown at about page 1072
    CCM-CBCMR is described at about page 1110

    The 4 clock selects come out to the different speeds:
    Code:
    		static const uint32_t clk_sel[4] = {664615384,  // PLL3 PFD1
    					     720000000,  // PLL3 PFD0
    					     528000000,  // PLL2
    					     396000000}; // PLL2 PFD2
    And the clock divider can be a value between 1-8

    So then the actual SPI speed is computed, by finding a divisor of the resultant above that gives us the highest rate it can that does not exceed the value you requested.

    Currently it looks like we initialize the CBCMR in SPIClas::begin:
    Code:
    	CCM_CBCMR = (CCM_CBCMR & ~(CCM_CBCMR_LPSPI_PODF_MASK | CCM_CBCMR_LPSPI_CLK_SEL_MASK)) |
    		CCM_CBCMR_LPSPI_PODF(6) | CCM_CBCMR_LPSPI_CLK_SEL(2); // pg 714
    You are free to update these two fields after this and the SPI.beginTransaction with an SPISettings will give you the setting based off of the current settings. Note: If you do an SPI.beginTranaction(SPISettings(12000000, MSBFIRST, SPI_MODE0);
    Then change the clock and then ask for the same speed, in this case 12mhz, it may not catch that something changed, so you may want to ask first for a different speed and then ask for the speed you want...

    FYI - disregard the page number mentioned in code as this is probably the page number of the first version of the 1052 manual and has not been updated to the 2nd (or more) edition of the 1062 pdf...

    Also don't remember why PODF=6 and CLK_SEL=2...

  3. #3
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by 1of9 View Post
    edit: looks like it is f_bus /2 = max spi clock so can you increase the f_bus w/o overclocking the cpu or is that the only way?
    If you're concerned about "overclocking", please consider the electrical specs datasheet (footnote under table 57 on page 67) says 30 MHz is the max SPI speed regardless of how you internally configure the chip.

    SPI probably can run faster (especially if the chip isn't used only near room temperature), but anything over 30 MHz is considered overclocking.

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    Quote Originally Posted by PaulStoffregen View Post
    If you're concerned about "overclocking", please consider the electrical specs datasheet (footnote under table 57 on page 67) says 30 MHz is the max SPI speed regardless of how you internally configure the chip.

    SPI probably can run faster (especially if the chip isn't used only near room temperature), but anything over 30 MHz is considered overclocking.
    I am trying to trace the code backwards and see what is going on, but if 30mhz is supposed to be the max spi, then it is "overclockable" out of the box because you can send in up to 38000000 into
    SPI.beginTranaction(SPISettings(38000000,..... and you get a faster clock (as confirmed by timing the code and looking at it on an oscilloscope). if you send > 38m in you don't get anything faster. I don't know if it is intentional or not that this is the way it currently works. The registers that control the spi clock are kind of cryptic and I don't really understand what each bit does.

  5. #5
    Senior Member+ KurtE's Avatar
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    Yep - they are sort of cryptic, which is why I pointed you back to PDF file for where the bits are defined and a sort of chart showing you how all of the clocks relate to each other...

    And I know there are some others who like to go as fast as possible, but I usually don't try to hit that high as things start not working as maybe my jumper wires are not short enough or ...

  6. #6
    Senior Member+ defragster's Avatar
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    I know I ran the one display (st7789) in a thread to 48 to 64 and saw faster throughput up to that speed on T4. It was hardcoded lower - probably to device spec - but going to a supported multiple and trying it is YMMV

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