Looks like fast SD modes are impossible with T 4.0. It would be great if a future version of of T 4.x with a builtin SD supported 1.8V signaling.

The uSDHC supports DDR50/SDR50/SDR104 with 1.8V signaling. I can put an SD in 1.8V mode with the uSDHC.

The problem is that switching from 3.3V to 1.8V signaling requires switching the GPIO power rail, NVCC_SD0, from 3.3V to 1.8V. This requires a 1.8V supply and switch.

The uSDHC controller assumes the NVCC_SD0 power on ball position J6 will be switched when the VSELECT bit is set/cleared in the uSDHC. VSELECT is associated with a GPIO pin.

A good choice for VSELECT is GPIO_B1_14.alt6 since that is the boot config. There are four choices so any would do.

I have been testing SdFat-beta on T4 and get these results for 512 byte reads/writes.
Code:
Default Speed mode: 3.3V signaling at 24.75‬ MHz.

write speed and latency
speed,max,min,avg
KB/Sec,usec,usec,usec
11312.22,84,44,44
11286.68,83,44,44

read speed and latency
speed,max,min,avg
KB/Sec,usec,usec,usec
11682.24,130,43,43
11709.60,130,43,43
Code:
High Speed mode: 3.3V signaling at49.5 MHz

FILE_SIZE_MB = 5
BUF_SIZE = 512 bytes

write speed and latency
speed,max,min,avg
KB/Sec,usec,usec,usec
22026.43,49,22,22
22026.43,48,22,22

read speed and latency
speed,max,min,avg
KB/Sec,usec,usec,usec
22624.43,754,22,22
22624.43,133,22,22
Doubling the clock increases the transfer rate by about 194%. It would be great to try SRD50 with 99 MHz clock or SDR104 with a 198 MHz clock.

SDR50 might get 40 MB/sec. Maybe 70 MB/sec with SDR104. The uSDHC supports infinite transfers. I have written 500 MB files with the SD seeing a single transfer.

SdFat-beta has optimize contiguous pre-allocate for both FAT and exFAT so no access to the FAT or bit map is required.

See the ExFatLogger example for details of preAllocate() and truncate().