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Thread: Teensy 3.5 or Teensy 4.0: Parallel Synchronous DMA output?

  1. #1
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    Teensy 3.5 or Teensy 4.0: Parallel Synchronous DMA output?

    I'm looking to push small (100-200 bytes) but very fast bursts of parallel 8-bit data using DMA on the Teensy 3.5 or (preferably) Teensy 4.0, but with a CLOCK pin to make the transfer synchronous. The closest existing library I can think of is OctoWS2811, but AFAIK that library doesn't have a CLOCK pin option.

    For Teensy 3.5: I am guessing I need to program a DMA channel to trigger off a timer output. Is there an existing library that makes this easy to set up?

    For Teensy 4.0: The massive speed increase of this CPU is tempting for many new projects. But I can't figure out which pins constitute one 8-bit parallel port for DMA output. (Maybe this is also why OctoWS2811 hasn't been supported for Teensy 4.0 yet?) Any hints which pin and which DMA reference can be used to make a synchronous interface?

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    The Teensy boards were not designed for parallel I/O, I don't think there are 8 adjacent bits available. You could piece together things in software but don't know how it would work under DMA control.

    See also: https://forum.pjrc.com/threads/57331...d-parallel-bus
    https://forum.pjrc.com/threads/57698...is-it-possible

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    [QUOTE=JBeale;216491]The Teensy boards were not designed for parallel I/O, I don't think there are 8 adjacent bits available.

    That's simply not true. The Teensy 3.1, 3.2, 3.5 and 3.6 boards all have PORT D bits 0-7 mapped, and their DMA use as an asynchronous parallel port (running at 800 khz) is the basis of Paul's OctoWS2811 library. Granted, the pins aren't "adjacent" physically on the Teensy boards. But parallel operation using DMA is definitely supported. (I'm less sure about the Teensy 4.0.)

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    Senior Member+ defragster's Avatar
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    [QUOTE=AleXYZ;216502]
    Quote Originally Posted by JBeale View Post
    The Teensy boards were not designed for parallel I/O, I don't think there are 8 adjacent bits available.

    That's simply not true. The Teensy 3.1, 3.2, 3.5 and 3.6 boards all have PORT D bits 0-7 mapped, and their DMA use as an asynchronous parallel port (running at 800 khz) is the basis of Paul's OctoWS2811 library. Granted, the pins aren't "adjacent" physically on the Teensy boards. But parallel operation using DMA is definitely supported. (I'm less sure about the Teensy 4.0.)
    @JBeale's note AFAIK reflects the primary concern of pin placement compatibility given the underlying MCU's functional units as presented to given pins. If getting pin placement compatibility broke up ports into tiny pieces that was compromised. That is parallel I/O groups were last on the list of what fits the best use - given the 'few' number of pins a Teensy 4.0 presents and the desired functionality - having 7 Serial UARTS, 3 SPI buses, SDIO pins, 2 CAN and 1 CANFD, multiple i2c buses where possible in expected 'UNO' positions with Analog grouped etc accounted for the pin routing.

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    Senior Member+ defragster's Avatar
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    On this thread - 12 bits written in parallel :: Parallel-IO-is-it-possible

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    Senior Member PaulStoffregen's Avatar
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    Teensy 4.0 does not have 8 continuous pins on any GPIO port. This was one of the painful trade-offs during the pre-beta discussion on assigning the pins and the changes made between the early 1052 and later 1062 beta. Teensy 4.0's GPIO peripheral also only supports 32 bit access, so even if you did have 8 pins, you might not be able to use it as you can with Teensy 3.x.

    However, clocked 8 bit parallel output might be possible on Teensy 4.0 using FlexIO. I must confess, I haven't actually written any FlexIO code yet. Kurt is really the only one here qualified to comment on this right now. Anyone can try to read the reference manual, but the FlexIO chapter is particularly difficult to read and scant on explanation of how it really works, except for the published examples.

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    Ouch, FlexIO solution sounds outside my pay grade. That puts the Teensy 4.0 out of the running for this application. For the time being.

    Can anyone point me in the right direction of setting up a Teensy 3.5 to DMA output to PORT D with a clock pin? Basically I'm feeding a high speed packet of data to an 8-bit wide shift register, 100-200 bits in length. Currently I'm doing this with interrupts but there's too much CPU usage and want to go the DMA route.

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    Thanks Paul,

    I have not tried anything like that yet with FlexIO. So far only done a couple of simple things like UART and SPI. It looks like they have examples emulating some busses like 8080... So it might be doable, but even if they were, would need to figure out if we have enough of the Flex IO pins configured to handle this or not...

    As for setting up DMA for SPI 3.5. I have only done it, when it relates to SPI, so hopefully someone else might help

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