It will be interesting to know how the 1170 handles the memory
Today with with 1062 we get 512K is TCM for M7 and the remaining 512K is accessed by slower AXI bus.
Soon with 1170, we'll get the same 512K as TCM for M7, and 256K as TCM for M4, and the remaining 1280K on AXI bus for both of them to use. The M7 side appears to be pretty much the same as we have now in Teensy 4.0, but with 1280K of OCRAM2 instead of only 512K, and of course 1 GHz clock.
The M4 situation with RAM is pretty similar to Teensy 3.6, except at 400 MHz. All of the 256K ram in Teensy 3.6 is TCM. The ram in Teensy 3.6 at 20000000 and above can be considered DTCM, and the ram at 1FFFFFFF and below can be considered ITCM. The M4 core uses 2 buses which map into those RAM banks. M4 has no separate bus for other stuff, so the situation isn't quite analogous to M7 with 3 buses.
On Teensy 3.6, we currently have an 8K cache for code, and there's no cache for data (and we don't have any other memory which could use such a cache). On 1170 we'll get a 16K cache for non-TCM code and 16K cache for non-TCM data, which is the 1280K of RAM shared between to M4 and M7. Historically we've never worried about caching on M4 because all memory was TCM or peripherals. But 1170 will bring 1280K of memory shared, with caching to manage on both sides.
On the 1280K shared RAM, it's not clear to me if it's all created equal. Looks like it may be in 3 independent banks, which is a good thing if you want to have both cores access the memory by their DMA controllers. Two banks of 512K may be intended for the M7 and the remaining smaller 256K bank may be intended for the M4. It's still not clear to me whether these RAM banks will truly support concurrent access. Seems like they should, but that might also be just wishful thinking on my part. The available info (even the stuff under NDA) isn't all that clear...
Every indication I'm seeing so far says the M7 core probably can not access the M4's 256K TCM, and the M4 probably can not access the M7's 512K TCM. So if you use only the M7, you get 1792K RAM, and if you use only the M4 you get 1536K.
Looks like there might also be some other small chunks of RAM, sort of like how we get an extra chunk of RAM in Teensy 3.6 for the FlexNVM and chunks of RAM in the CAN controllers on Teensy 4.0. But even if the early info weren't under NDA, it's so obviously a copy & paste job from other NXP chips that I would would wait until we have the real hardware to check.
But the main info is clear. M7 gets 512K TCM, same as we have now on Teensy 4.0, the M4 gets 256K TCM similar to what we have now on Teensy 3.6, and the remaining 1280K will be a big pool of somewhat slower memory shared between to 2 cores. Both have caching for that 1280K, so cache management functions will be needed on both sides.