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Thread: Future Teensy features & pinout

  1. #126
    Junior Member ProfHuster's Avatar
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    I want to upvote the posts about using the on-chip DAC. I am doing some high speed modulation, so the forum solutions of using external audio dacs will not help me. For example I would like to create a user specified sinewave in the 1+ MHz range. It is possible with the 3.2 using the direct write to the DAC using DAC0_DAT0 ...

    Now I have a question about the 4.0: Can the 4.0 chip/board be hacked to access the internal 12-bit DAC?

    Thanks, Paul, for your great work.

  2. #127
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by ProfHuster View Post
    Now I have a question about the 4.0: Can the 4.0 chip/board be hacked to access the internal 12-bit DAC?
    There is no 12 bit DAC on Teensy 4.0. NXP didn't put that hardware into the IMXRT1062 chip. No amount of software trickery can create a true analog output where the hardware simply does not exist. The closest possible is using fast digital PWM or MQS and then low-pass filtering the pulses.

    NXP is saying the 1170 chip will have one 12 bit DAC, so we can at least look forward to having this hardware again.

  3. #128
    Senior Member+ Frank B's Avatar
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    Quote Originally Posted by ProfHuster View Post
    I want to upvote the posts about using the on-chip DAC. I am doing some high speed modulation, so the forum solutions of using external audio dacs will not help me. For example I would like to create a user specified sinewave in the 1+ MHz range. It is possible with the 3.2 using the direct write to the DAC using DAC0_DAT0 ...
    How do you get correct timing without glitches? As I understand you, you use a simple loop? Or do you use DMA and a timer?

  4. #129
    Senior Member+ Frank B's Avatar
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    And I would be interested to know who started the rumor that the T4 has DACs. A DAC wasn't mentioned anywhere. But a lot of people have been asking when they're gonna be activated.

  5. #130
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    Quote Originally Posted by Frank B View Post
    And I would be interested to know who started the rumor that the T4 has DACs. A DAC wasn't mentioned anywhere. But a lot of people have been asking when they're gonna be activated.
    My suspicion is that it may be due to the Audio GUI tool. I think people see DAC listed there and assume it must be supported on the newest platform.

  6. #131
    Senior Member+ Frank B's Avatar
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    Oh, quite possible.

  7. #132
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    Quote Originally Posted by wcalvert View Post
    My suspicion is that it may be due to the Audio GUI tool. I think people see DAC listed there and assume it must be supported on the newest platform.
    I suspect this is the case as well. Perhaps a simple edit to the description would be helpful. Relatedly, is development of t4 as usb audio out on the dev roadmap?

    [EDIT]

    ah, just saw this: forum.pjrc.com/threads/57628-Any-work-with-USB-audio

  8. #133
    Senior Member PaulStoffregen's Avatar
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    Looks like I need to add a "boards supported" part to all the documentation panels in the design tool.

    Also on my todo list is adding the Teensy 4.0 only features, like I2S2.

  9. #134
    Junior Member ProfHuster's Avatar
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    Thanks for the answer. I was wondering *why* the DAC wasn't exposed, so you answered my question; there is no DAC.

  10. #135
    Quote Originally Posted by MichaelMeissner View Post
    While I've only done light displays for a 30-60 LEDs, it would be nice if there was some support for having something like a 74AHCT125 to bring out some WS2812B's or APA102's. I haven't seen much talk about the large displays for some time, but it may make sense to lay things out so you could do a new Octows2811 board. But maybe people have moved away from boards like Teensy, and now use other solutions.
    I've done several projects using Teensy 3.2 and strands of 144 APA102's. Each project had a 74AHCT125 to level-translate. It would be great if there were two pins of 5v level output for the APA102's, one for clock, one for data. One pin isn't enough for the APA102.

  11. #136
    Senior Member+ MichaelMeissner's Avatar
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    Quote Originally Posted by dundakitty View Post
    I've done several projects using Teensy 3.2 and strands of 144 APA102's. Each project had a 74AHCT125 to level-translate. It would be great if there were two pins of 5v level output for the APA102's, one for clock, one for data. One pin isn't enough for the APA102.
    Providing you aren't trying to use a SPI device (which also wants to use pins 11 and 13), you could use a LC prop shield, but that is rather expensive compared to a 74AHCT125.

  12. #137
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    Please, just run all the pins out.

    Click image for larger version. 

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    Everyone will be happy!

  13. #138
    Quote Originally Posted by Stradm View Post
    Please, just run all the pins out.

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    Everyone will be happy!
    Nop.
    The 3.6 format is quite good. Three rows make it very tall.
    Why not two but no more.

  14. #139
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    I posted this earlier, before I found all (some) of the discussion on this topic. I think it is actually the way to go, but everyone has an opinion. It is just so frustrating to have everything you want right there, but it does not work because of a few pins. And it is impossible to DIY this chip.
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  15. #140
    Senior Member+ KurtE's Avatar
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    Sorry I don't mean to be pessimistic about these ideas, but I am pretty sure it is unlikely that PJRC will come out with a new T3.6 with double or three rows of pins on a side.

    And as already mentioned in other recently closed thread that there will most likely be a T4 in the form factor very similar to the T3.6. At least for the exterior pins and SDCard... I am sure Paul will release to us more details when he is ready to.

    My guess is it is unlikely that PJRC will ship a double row T4.x Could be wrong, but my gut says improbable.

  16. #141
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    What is really needed is that the Muxs and XBar cross bridges need to be able to re-route the signals to/from nearly any pin. There is a lot of talk of flexability in the manual, but in the end somewhat limited actual options.

  17. #142
    Senior Member+ defragster's Avatar
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    This thread is for the yet unreleased 1170 processor - and it seems it was noted that it may have a new PCB form factor to support the twin core and accommodating a larger CPU die with 290+ (?) pins and present a usably complete set of features the 1170 offers that PJRC can support.

  18. #143
    Junior Member ProfHuster's Avatar
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    Quote Originally Posted by Frank B View Post
    How do you get correct timing without glitches? As I understand you, you use a simple loop? Or do you use DMA and a timer?
    I used DMA and a timer.

  19. #144
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by KurtE View Post
    My guess is it is unlikely that PJRC will ship a double row T4.x
    For the 1170, which isn't expected until the end of 2020 or perhaps early 2021, I am indeed considering double rows. I'm also watching for what happens with Arduino's high density connectors on Portenta H7. A longer form factor is also possible. At this point, decisions about that fairly far future board are still wide open. That's why this thread is still open. I am listening to feedback. This thread is about the 1170 board. I'd like to ask everyone commenting here to please stay on-topic about 1170.

    I can confirm PJRC will release another 1062-based board in the Teensy 3.6 form factor. It was discussed and feedback was sought in that now-closed "Pins to bring out on a hypothetical larger Teensy4" thread. All the public info is on that thread. The design is finalized, so no more feedback is possible on that board (which why that thread was closed). NO MORE INFO will be published until the product is released. I don't have a clear time frame when it will be ready. We're currently waiting on several parts. Even though Teensy is assembled in the USA, many of the parts we buy are manufactured in China. The recent COVID-19 / coronavirus quarantines may or may not be impacting the time frame. We just don't have clear info yet. Please be patient.

    Please do not hit me up for early pre-release info. As you can see on github and several threads on this forum, I'm taking this waiting-for-hardware time to work on many software features, which will soon begin beta testing. The very best thing you can do to help, apart from writing code, is installing and using the beta test versions as soon as they're available. Quick feedback on beta tests *really* helps.

    I also do try to listen to feedback on pinouts, form factors and other issues. That's why this thread exists.

  20. #145
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    That's great to know that the next gen 1170 may have more pins, one way or another. I photoshopped the 3.6/4.0 because the images were available, not because I thought those boards should be updated.

  21. #146
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    Using high density connectors like the one on the Portenta H7 is going to make prototyping an add on board quite difficult. Not only the fine pitch but spacing between the two connector is quite difficult to achieve accurately.

    Double row of 0.1" might be a good option. I've seen this used in a commercial board like this one:
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    Notice the connector is a SMD one, so more board space on the top layer.

  22. #147
    Senior Member+ mjs513's Avatar
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    I think going with the double row of 0.1 in pins would be better an idea at least from a DIYers perspective.

  23. #148
    Senior Member+ Theremingenieur's Avatar
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    I’d also vote for double rows in 0.1” spacing with the most common and Arduino pin out-alike signals on the inner rows, so that bread boarding in the classic Teensy style (perhaps even 3.2 or 4.0 pin compatible) could be done by only soldering pins there. Those who need more, specific, or less common signals could then solder pins to the outer row, but upwards and use DuPont wires to connect to other places on the breadboard without interfering. When, after the prototyping phase, it comes to design your own PCB, the double row solution might allow smaller solutions using double row headers than an endless long single row board.

  24. #149
    Senior Member+ defragster's Avatar
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    0.1's not as compact - but Much more durable and easy to solder and work with.

    Perhaps the outer row each side could be run to common edge through hole pins - if like p#146 One outer row on each side could be COMMON pins shared with the outer row of the connector the inner row on each side could be unique for use on a daughter board or wiring. And if spaced right could span TWO breadboards for lots of work room.

  25. #150
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    The Pyboard D-series uses an interesting concept. Big thru holes at 0.1" pitch then smaller holes between the 0.1" hole. Making the pitch 0.05".
    You can get 0.05" pin header and sockets from Mouser.

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