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Thread: I2S: How to set the BCLK to LRCLK ratio?

  1. #1
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    I2S: How to set the BCLK to LRCLK ratio?

    Hello,

    I just bought myself a ADC board with a AK5720 chip, using it to input audio into the Teensy 4.0 via I2S. In the datasheet it says one has to insert a clock ratio of BLCK/LRCLK=32fs to get 16bit output instead of 24bit. When i measured with an oscilloscope, the ratio by default was 64fs..
    Does anyone know how to change the BLCK speed to a lower frequency?

    Greetings from germany,
    Chris

  2. #2
    Senior Member PaulStoffregen's Avatar
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    Most I2S chips automatically ignore the extra bits when the ratio is higher. Maybe this chip will do that too?

    Controlling this ratio is difficult. It's not a simple parameter you can just set. It requires carefully redesigning how the I2S hardware and DMA transfers are configured.

    Long ago all the I2S code used a ratio of 32. The I2S quad input still does have a ratio of 32, so the first easy thing to try would be using the quad input and simply don't connect the other data pin and just use only 2 of the 4 channels.

    If that works and a ratio of 64 does not work (which seems unlikely - so far nobody has found a chip which actually requires 32), and if using the quad input isn't a good solution, you might look through github's history for the very old I2S code. The MEMS microphones do require a ratio of 64, and almost all chips default to using 64, which is the reason we switched to BCLK/LRCLK=64.

  3. #3
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    Hey Paul,

    thanks for the reply!

    As far as I understand, this particular chip needs a ratio of 32fs to output 16 bit data. At least that's written in the datasheet on page 16, last row: "Note 12. SDTO outputs 16-bit data when BICK=32fs."
    (https://www.google.com/url?sa=t&rct=...LtcOtlXy9OOUW0)

    It seems to work somehow with normal settings, but even at a very low input volume (like 50mVss or so) the maximum amplitude in Teensy is reached, while theoretically this should be the case at voltages roughly 100 times higher. This made me think that maybe Teensy only reads the 16 LSB of a 24 bit Stream from the chip?

    However, tried i2SQuad (which couldn't compile for some reason for teensy 4.0, but with a Teensy 3.2 it worked). It brought only a completely loud noise, more or less. My measurement with a scope still showed a ratio of 64fs in quad mode btw..

    As i find the module quite appealing (I got it from here: https://www.audiophonics.fr/en/diy-d...fast_search=fs) I will still not give up quickly and try to work through the cores. Any suggestions where exactly to start? Audio Library -> InputI2S or something?

    Greets
    Chris

  4. #4
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    Strangely, when I connect the ADC Module at the same time with a Teensy audio shield, it works as it should like I just found out..

  5. #5
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by Chris314 View Post
    This made me think that maybe Teensy only reads the 16 LSB of a 24 bit Stream from the chip?
    I2S is well defined. The MSB is always 1 clock cycle after LRCLK changes. Teensy reads the first 16 bits starting there. In stereo I2S which uses ratio 64, Teensy ignores the next 16 bits, which are supposed to be the 8 low bits and 8 unused bits.

    Looked briefly at the datasheet. It seems to say this chip supports either 32 or 48 & higher, in table 2 on page 16.

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    Any chance the chip is connected in one of those other modes? Of the 12 modes this chip supports, you definitely should be using it in I2S slave mode (mode #1 in that table), since Teensy's normal mode is I2S master.

  6. #6
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    Thank you very much, Paul! Selecting mode 1 seems to do the trick - think the board had the chip in mode 3 by default. Because I couldn't figure out how the CKS-pin was connectet to VCC on the PCB, I simply desoldered it and connected it to GND with the green wire in the photo. Now it works perfectly.

    Click image for larger version. 

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    Greetings, Chris

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