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Thread: FlexIO in Teensy 4.0

  1. #1

    FlexIO in Teensy 4.0

    Hi, I'm embarking on an ultrasound project in which I was hoping to use the FlexIO module to implement a custom SPI interface to feed waveform data to one of an array of external circular shift registers. Basically I need to send 192 bits of data on a custom clock frequency generated by an eFlexPWM(7.68MHz). The datasheet says there are 3 banks of FlexIOs, FlexIO1, FlexIO2, and FlexIO3, where FlexIO1 has 16 pins and FlexIO2-3 have 32pins. The datasheet then goes on to describe a single module as a shift register which can be tied to others to form a larger shift register. However, it seems like there are only 12 32bit shift registers total, each in banks of 4. I need 6 32 -bitregisters tied together for 192 bits, is this possible?

    The clock cycles for the shifting are also used for driving the ultrasound signal, so once the signal to send is set, the I need 1 bit going out on every clock pulse.

    Big picture-wise, the Teensy will send updated waveform data one at a time to each circular shift register, which in turn drive an array of ultrasonic transducers, with the goal of being able to drive anywhere from 8 to 1024 transducers in a phased array. Since the clock signals are hardware generated and the Teensy is only used to update waveforms rather than drive them all, the processor should be free to do others stuff.

  2. #2
    Senior Member+ KurtE's Avatar
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    Jan 2014
    Sorry I have no idea of how you can chain all of the shift registers together that big. However I am also not sure you need to? Why can you not simply shift in 8 or 16 or 32 bits at a time and construct your 192 bits from several of these shifts?

    I have played around with some of it and have a played around some more with logical UARTS, but also some with SPI, including some with DMA with the SPI...

    I believe some of the details of what I was playing with is up on the thread:

    Also you might do some more searching on thread as looks like a few others have done some stuff with FlexIO

  3. #3
    Thanks for the input, I'm trying to work my way through setting up FlexIO to tinker with the possibilities. There's quite a few ways to implement the general concept, but I figured I'd give it a shot at just using the Teensy hardware to lower the BOM.

    Shifts are to be timed with the state of the data in the recirculating registers, so it's possible that with counting a transfer delay you could inject the partial data fragments in the right position on subsequent re-circulations.

    If you can set the input to SHIFTERi to be the output of SHIFTER(i+1), and there are 4 shifters in a flexIO, any idea what the result of setting the input of SHIFTER3 to the output SHIFTER(i+1) is? Seems to me it could be unconnected, the output of SHIFTER0 in the same flexIO, or possibly (fingers crossed) the output of shifter0 in another flexIO.

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