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Thread: 5 MSPS or higher 8-bit ADC and delayed playback via R2R ladder

  1. #1

    5 MSPS or higher 8-bit ADC and delayed playback via R2R ladder

    This is what I need to realize:

    1. Digitize an incoming 'chirp' consisting of 1 microsecond pulses of varying amplitude between +/- 1VDC (2VDC p-p) @ 5 Mega Samples Per Second (MSPS) and store the values to RAM. The chirps repeat every, say 500 to 1200 microseconds, signaled by a 1 us sync pulse on another line. This sync pulse can be taken as a reference for the start of digitization.

    2. After a delay of, say 368 microseconds, reproduce the digitized data in RAM, back to the +/- 1VDC chirp @ 5 MSPS, via an R2R ladder or DAC.

    3. Meanwhile, while the first lot of data from the first chirp is being reproduced after a set delay, a new chirp comes up for digitization... and so on.

    My questions:

    (a) Can the Teensy 4.0 ADC digitize at 5 MSPS? Can it do better than that, so I get higher resolution?
    (b) Is the Teensy 4.0 GPIO laid out in port-wise fashion, that can enable parallel data to be exchanged with a 2nd Teensy, without losing cycles to shifting and other boolean tricks to exchange an 8-bit word between GPIOs?
    (b) I have no problem using dual Teensy 4s to realize this - one for digitizing the data and parallel transfer to the 2nd Teensy. And the 2nd Teensy for reproducing the 'chirp' after the preset delay. The sync pulse will keep the two in sync.

    I come from Arduino, ESP32 and Raspberry Pi and this is the first time I will be using a Teensy 4.0. I look forward to advice on how to tackle this project with the Teensy 4.0, which seems to me, the only solution.

  2. #2
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    The fastest conversion time I see in the datasheet is .7usec. Not fast enough, even if you alternated between ADCs.

    You could use 5 sample and holds and then convert analog to digital at a much slower rate.

    I don't see a need for more than one MCU.

  3. #3
    Quote Originally Posted by jonr View Post
    The fastest conversion time I see in the datasheet is .7usec. Not fast enough, even if you alternated between ADCs.

    You could use 5 sample and holds and then convert analog to digital at a much slower rate.

    I don't see a need for more than one MCU.
    Thank you for the response, @jonr.

    I scanned the datasheet but haven't yet been able to find the ADC details.

    What if I used an external, parallel 8-bit ADC with an external clock input and used the same clock input for an external interrupt on the Teensy? Is there a diagram somewhere, that maps the Teensy 4.0 pins and the iMXRT1062 pins? Is there a port-oriented layout for the M7 pins? Or is each pin to be manipulated to yield a byte? - that would lose a lot of instruction cycles...

  4. #4
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    The teensy 4 is very fast - you have far more than enough instructions in .2 usec to not worry about the speed of constructing a byte from bits. But yes, I expect that there is a register you could read to get the status of 8 properly chosen GPIO pins in a single operation.

    A fast, 8 bit, parallel output ADC is a viable alternative to 5 sample (or track) and holds. Would be interesting to determine just how many samples/sec are possible.

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