Hi All.

I have a need in my project to periodically switch the timing source (on the fly) of the I2S Tx from an externally supplied MCLK to the internal one generated by Fractional Clock Divider -- and back again. It looks like the MOE field of the MCR register will do this for me. At the same time, I'd switch the MUX for the MCLK pin so the internally generated signal doesn't clash with the external MCLK source which will still be physically connected.

The only question I have is related to this note in the MOE field's description (K20 Datasheet):

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I couldn't find a bit field that explicitly disables the MCLK divider, so I'm wondering what that statement actually means.

Thanks.