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Thread: ADC schematic T4

  1. #1
    Junior Member
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    ADC schematic T4

    Hi everyone!
    I'm working on a race car project and i was wondering about the adc schematic for T4, I need to choose a capacitor for voltage divider so i need first to know the value of resistance of adc when it is sampling

    Anyone who knows something about that?

  2. #2
    Senior Member+ Theremingenieur's Avatar
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    There is a Kinetis application note about the ADCs on the NXP website. These Delta-Sigma ADCs do NOT have a constant input impedance since each conversion cycle starts with loading an internal capacitor (low impedance, drawing high current from the source) while afterwards, it goes back into high impedance state. Best is to design your voltage divider independently and use a rail-to-rail op-amp as voltage follower afterwards between your divider and the ADC.

  3. #3
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    Keep ADC input resistance below 4K ohms. You can put a 0.01 F capacitor on the input pin to reduce noise (but it effects bandwidth unless you go down to more like 40 ohms).

  4. #4
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    Thx for your tips!
    I will go for rail-to-rail op-amp voltage follower since it is very critical to read the data from the sensors.

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