There is a Kinetis application note about the ADCs on the NXP website. These Delta-Sigma ADCs do NOT have a constant input impedance since each conversion cycle starts with loading an internal capacitor (low impedance, drawing high current from the source) while afterwards, it goes back into high impedance state. Best is to design your voltage divider independently and use a rail-to-rail op-amp as voltage follower afterwards between your divider and the ADC.