Does anyone have a suggestion on what mechanism to use to accomplish this on a Teensy 3.6?

Send a predefined sine wave out SPI to a 4 channel DAC (AD5664R) at a set data rate (frequency). Each DAC channel takes 24 bits of data with an active low sync to store and update the DAC values.

Similar to doing the same thing with DMA with the ability to set PDB0_MOD value to control timing.

I looked at DmaSpi but I am not finding a way to set the data path to 24 bits in conjunction with the ActiveLowChipSelect class to manage the sync (CS) line.