I want to test wich influence caching has on the Teensy 4.0. I use the following routine (taken from CMSIS) to disable caches:
Then I execute a FFT routine with and without cache. I can measure no difference in runtime. I this because data and instructions are stored in on-chip RAM? How could I demonstrate cache behaviour?
Code:
// from core_cm7.h (CMSIS)
#if defined(__IMXRT1062__)
#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
#endif
#define SCB_ID_CSSELR1 (*( uint32_t *)0xE000ED84) // Cache Size Selection
static inline void SCB_DisableDCache (void){
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB_ID_CSSELR1 = (0U << 1U) | 0U;
asm("dsb");
ccsidr = SCB_ID_CCSIDR ;
SCB_CCR &= ~(uint32_t)SCB_CCR_DC ; /* disable D-Cache */
// clean & invalidate D-Cache
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB_CACHE_DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
// __schedule_barrier();
asm("nop");
asm("nop");
} while (ways--);
} while(sets--);
asm("dsb");
asm("isb");
}
static inline void SCB_DisableICache (void){
asm("dsb");
asm("isb");
SCB_CCR &= ~(uint32_t)SCB_CCR_IC ; /* disable I-Cache */
SCB_CACHE_ICIALLU = 0UL; /* invalidate I-Cache */
asm("dsb");
asm("isb");
}