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Thread: testing data- and instruction-cache on the Teensy 4.0

  1. #1
    Senior Member
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    Feb 2019
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    testing data- and instruction-cache on the Teensy 4.0

    I want to test wich influence caching has on the Teensy 4.0. I use the following routine (taken from CMSIS) to disable caches:

    Code:
    // from core_cm7.h (CMSIS)
    #if defined(__IMXRT1062__)
    #define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
    #define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
    #define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
    #define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
    #define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
    #define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)
    #define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
    #define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
    /* Cache Size ID Register Macros */
    #define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
    #define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
    #endif
    
    #define SCB_ID_CSSELR1    (*( uint32_t *)0xE000ED84) // Cache Size Selection
    
    static inline void SCB_DisableDCache (void){
        uint32_t ccsidr;
        uint32_t sets;
        uint32_t ways;
        SCB_ID_CSSELR1 = (0U << 1U) | 0U;  
        asm("dsb");
        ccsidr = SCB_ID_CCSIDR ;
        SCB_CCR &= ~(uint32_t)SCB_CCR_DC ;  /* disable D-Cache */
                                               // clean & invalidate D-Cache 
        sets = (uint32_t)(CCSIDR_SETS(ccsidr));
        do {
          ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
          do {
            SCB_CACHE_DCCISW  = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
                           ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
            //  __schedule_barrier();
              asm("nop");
              asm("nop");
          } while (ways--);
        } while(sets--);
        asm("dsb");
        asm("isb");
    }
    
    static inline void SCB_DisableICache (void){
        asm("dsb");
        asm("isb");
        SCB_CCR &= ~(uint32_t)SCB_CCR_IC  ;  /* disable I-Cache */
        SCB_CACHE_ICIALLU = 0UL;                     /* invalidate I-Cache */
        asm("dsb");
        asm("isb");
    }
    Then I execute a FFT routine with and without cache. I can measure no difference in runtime. I this because data and instructions are stored in on-chip RAM? How could I demonstrate cache behaviour?

  2. #2
    Senior Member+ Frank B's Avatar
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    Location
    Germany NRW
    Posts
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    Exactly, it gets copied to RAM. This happens in startup.c.
    If you don't want this - which is good for initialization functions which run only once for example, you can use the FLASHMEM define.

    FLASHMEM void func(void) {
    Or, for data:
    PROGMEM int data[...

  3. #3
    Senior Member+ manitou's Avatar
    Join Date
    Jan 2013
    Posts
    2,558
    FWIW, there were discussions on T4 cache behavior in giant Teensy 4 beta thread, e.g.
    https://forum.pjrc.com/threads/54711...l=1#post197430

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