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Thread: Are SPI3 and SPI4 accessible? Can both MOSI & MISO be used to x-mit simultaneously?

  1. #1
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    Are SPI3 and SPI4 accessible? Can both MOSI & MISO be used to x-mit simultaneously?

    I was looking through the (Teensy 4) core code and noticed the definitions for SPI3 and SPI4 were defined. Is it possible to use the pin muxing on the Teensy to make the pins for SPI3 and SPI4 accessible? For my current project, I only need MOSI. Also, I think I read that I can reverse the direction of MISO and use that pin as an output. Can both RX and TX pins on the same SPI be used simultaneously for two different external devices? I haven't dug in to see how the transmit data bits are shifted out... do they come from two different buffers or are the bits alternated (being shifted out from one buffer)?

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    After a bit of digging, I see the the Teensy 4.0 SPI Library "maps" the internal LPSPI-4 to the external pins on the Teensy for SPI (CS:pin10,MOSI:pin11,MISO:pin12,SCK:pin13). LPSPI-3 is mapped to the external pins on the Teensy for SPI1 (MOSI1:pin26,SCK1:pin27). LPSPI-1 is mapped to the external pins on the Teensy for SPI2 (CS2:pin36,MOSI2:pin34,MISO2:pin35,SCK2:pin37).

    I assume this was done by the designers for great reasons (e.g. backward compatibility, maximize offerings of the Teensy 4 while dealing with the complexity of all the possible ways to design it).

    Teensy 4 offers us three MOSI pins, which I listed above, and that is enough for my current project. I did read enough to learn that the IOMUX capability is very extensive, so it may be possible to move things around to get access to LPSPI-2, but (1) figuring that out with enough detail and confidence is a challenge for noobs like me, and (2) if I did figure out something that get gave access to LPSPI-2 it would likely constrain other existing elements on the Teensy (i.e. stop those things from working).
    Last edited by defragster; 02-09-2020 at 01:45 AM. Reason: turn off smilies

  3. #3
    Senior Member+ defragster's Avatar
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    The Teensy card summarizes available function through the MUX on that pin.

    Features not available to a pin can't pull from another pin - unless it is a FLEX pin that can offer that function.

    The Teensy 4 has a larger number of pins than prior Teensys - and it seems functions were widely distributed, so ALT ( denoted in grayed text ) are more common on the T_3.x family and at a glance only 4 pins have grayed text - none are MOSI/MISO pins.

    Other than the RefMan - there are two or three forum user summaries of pin functions that may detail them in a more tabular fashion. Maybe a post on the T_4 beta thread.

  4. #4
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by JimKazmer View Post
    maximize offerings of the Teensy 4 while dealing with the complexity of all the possible ways to design it
    Yes, this.

    Somewhere on this forum is an old thread (from before the huge T4 beta test thread) about choosing which pins to bring out. Because this chip offers so many amazing peripherals and we have only 24 outside edge pins and 16 more SMT pads on the bottom, difficult choices and trade-offs had to be made. Access to the many serial ports, CAN buses, I2C, analog inputs, I2S digital audio and other pins were considered important. Proving more SPI pins would have meant sacrificing some of other other critically important features.

    In the middle of the beta test, where we switched from the 1052 to 1062 chip, some minor changes were made to the pins to gain access to CAN3, because it's the only CAN port with CANFD. The decision was made to sacrifice the 8th serial port to keep access to SPI1.

    Anyway, if you're looking to do special things with SPI, you might also look at the FlexIO peripheral. There are 3 of those. Each can implement SPI (and other serial protocols). Only the first 2 FlexIO have DMA. All 3 can be used by conventional register access.

  5. #5
    Senior Member+ defragster's Avatar
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    This thread :: Teensy-4-0-(hypothetical)-pin-assignments

    preceded this T4 beta test thread: Teensy-4-0-First-Beta-Test

    Looked at nxp imxrt model summary - so glad the 1062 worked out versus the 1052's 512 KB total RAM, and anything short of the 1052 really loses a lot of cool things in the T_4 and suggested T_4.1

    Saw a note that somebody playing with display graphics had to FLASHMEM some code to get a running sketch when debug was enabled so code and data fit in lower 512KB RAM1
    Last edited by defragster; 02-09-2020 at 08:34 AM.

  6. #6
    Senior Member+ KurtE's Avatar
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    As already mentioned, only 3 of the 4 SPI sets of pins are available on the T4. As Paul mentioned, you can emulate SPI using FlexIO. I have a version of doing that up on my Github project: https://github.com/KurtE/FlexIO_t4

    One complexity of trying to make another SPI using FlexIO, is you will have to modify any code that was setup to use SPI to use a different code base, as a large percentage of libraries are setup to only handle SPI, and those that can handle different SPI objects, typically do this, by allowing the user to specify a pointer or reference to an object of the SPIClass. And my FlexIO SPI code is not a member of this class and as the member functions of the SPIClass are not virtual, I don't know of any clean way to subclass them.

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