This sounds awesome... Loading the SPI transmit buffer with a pre-defined message that you want to repeat, setting one bit (CIRFIFO - Circular FIFO Enable) in a configuration register, and then initiate your transfer... The message is repeatedly sent without having to tie-up any interrupts, DMA, polling, or checking status registers. Well, it sounds great to me, but I haven't gotten it to work. It seems like certain error flags are raised that stop the SPI from doing the circular loop. Seems like there are some details missing from Chapter 47 of the "i.MX RT1060 Processor Reference Manual, Rev. 1, 12/2018" (see pages 2933, 2946, 2497).
I'll try to clean up my code and post it... its a bit of a hack of the existing core SPI libraries. I was hoping to reduce it to a sequence of register writes.
Any insights or other information would be appreciated.
I'll try to clean up my code and post it... its a bit of a hack of the existing core SPI libraries. I was hoping to reduce it to a sequence of register writes.
Any insights or other information would be appreciated.