Clock generation unit on Teensy 4.0

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ossi

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I currently look into the clock generation unit of the Teensy 4.0. I want to know how this works, but its very very complex. Are there anywhere examples how to set the various options? Has someone hints for me?
 
Maybe look at the startup code, which configures the main 3 PLLs and most essential parts.

https://github.com/PaulStoffregen/cores/blob/master/teensy4/startup.c

https://github.com/PaulStoffregen/cores/blob/master/teensy4/clockspeed.c

For the rest, look in the code for each peripheral.

Audio lib has code for PLL4.

https://github.com/PaulStoffregen/Audio/blob/master/utility/imxrt_hw.cpp#L34

USBHost_t36 has code for PLL7.

https://github.com/PaulStoffregen/USBHost_t36/blob/master/ehci.cpp#L168

So far there's no code published for PLL5 (video) and PLL6 (ethernet).

All the other peripherals are relatively simple, usually just configuring a mux to choose one of the PLL outputs, and dividers to get it into the right range. If you really want to see that code, just look at libs like SPI, Wire, FlexCAN_t4, etc.

Some peripherals like FlexPWM are fixed to run only from the peripheral clock. For those, config is just a matter of enabling their clock in the clock gate registers. Simple stuff.
 
Hi Paul, thanks for your hints. Momentarily I am trying to understand the clocking and sampling of the ADC. Is it right that changing the CPU clock speed will also change the clock conversion time?
 
There is a nice picture on Page 1016/17
Looks like it is connected to IGP which is CPU-Clock dependent
 
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