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Thread: ADC async clock generation Teensy 4.0

  1. #1
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    ADC async clock generation Teensy 4.0

    The Teensy 4.0 cpu datasheet claims to have a "Asynchronous clock source for lower noise operation with option to output the clock". I can not find this clock source described in the datasheet. Does someone know where to get info?

  2. #2
    Senior Member+ Frank B's Avatar
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    if the spread spectrum option is meant, look for "528MHz System PLL Spread Spectrum Register"
    Quote Originally Posted by Reference Manual
    14.6.1.3.2 System PLL (PLL2)
    This PLL synthesizes a low jitter clock from the 24 MHz reference clock. The PLL has
    one output clock, plus 4 PFD outputs. The System PLL supports spread spectrum
    modulation for use in applications to minimize radiated emissions. The spread spectrum
    PLL output clock is frequency modulated so that the energy is spread over a wider
    bandwidth, thereby reducing peak radiated emissions. Due to this feature support, the
    associated lock time of this PLL is longer than other PLLs in the SoC that do not support
    spread spectrum modulation.
    Spread spectrum operation is controlled by configuring the
    CCM_ANALOG_PLL_SYS_SS register.

  3. #3
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    I don't remember it exactly, but I think that information is in the electrical specs sheet. For the Teensy 4 the asynch clock can run at 10 or 20 MHz.

  4. #4
    Senior Member duff's Avatar
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    If ADCx_CFG[ADHSC] registor is 0 then it's 10MHz if it's 1 then it's 20MHz. ref: https://www.nxp.com/docs/en/nxp/data...XRT1060CEC.pdf

  5. #5
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    Thanks for your help! Now I have the info I needed.

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