How to flush cache on T4 (for DMAMEM)?

[JarkkoL]

Hi,

I read from the T4 memory layout specs section that DMAMEM specified buffers needs to be flushed for DMA transfer because RAM2 is cached. Is there documentation about these "cache management functions" somewhere?

Currently without DMAMEM my DMA transfer works quite fine, but with DMAMEM it's totally corrupted.

Thanks, Jarkko

 

[KurtE]

You might look at https://forum.pjrc.com/threads/54711-Teensy-4-0-First-Beta-Test?p=209340&viewfull=1#post209340

 

[JarkkoL]

Cool thanks, works!