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Thread: I2S input connections confusion: BM23 and Teensy 3.6

  1. #1
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    I2S input connections confusion: BM23 and Teensy 3.6

    I am designing a bluetooth soundbar + audio visualizer using Teensy. For BT and aux support, I intend to use the BM23 , which provides 16 bit, 44.1k audio via I2S. This is my basic block diagram:
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    The BM23 is replacing the audio shield, but I have not been able to reconcile its desired pinout (below - page 18 in datasheet linked above; BLCK, DACLRC, ADCDAT, DACDAT) with Teensy's (BCLK, MCLK, RX, LRCLK).

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    These are my questions:
    1. Am I definitely using the BM23 in slave mode? Why would I use it in Master mode?
    2. If in Master mode, should the RFS0 pin be TFS0 (ie is there a mistake in the datasheet fig. 2-8)?
    3. I think BCLK ~ BCLK and DACLRC ~ LRCLK, but how do ADCDAT and DACDAT correspond to MCLK and RX? Do they at all?
    4. Am I constrained to 16bit, 44.1k? Can I use 24bit or 48k?


    Thanks for any help! All the different labels have been pretty confusing.
    Last edited by cdh; 03-23-2020 at 10:15 PM. Reason: added reference to datasheet page

  2. #2
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    Quote Originally Posted by cdh View Post
    [*] Am I definitely using the BM23 in slave mode? Why would I use it in Master mode?
    The mode is controlled by configuration of the device, the proper connections to use follow from that. Master mode would be required if you're using a DAC that only supports slave mode.

    [*] If in Master mode, should the RFS0 pin be TFS0 (ie is there a mistake in the datasheet fig. 2-8)?
    I'd use Slave mode and have T3.6 be Master.

    [*] I think BCLK ~ BCLK and DACLRC ~ LRCLK, but how do ADCDAT and DACDAT correspond to MCLK and RX? Do they at all?
    It looks to me like there's a contradiction between the diagram you posted and the pin assignment table on Page 10 of the Datasheet:

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    Either DR0 or DT0 is the I2S data from the BM23 to the T3.6. That's the one you want to connect to I2S0_RXD0 (T3.6 Pin 13). My guess is that the block diagram is wrong and the Table 1-2 is correct. It looks like BM23 does not require MCLK.

    [*] Am I constrained to 16bit, 44.1k? Can I use 24bit or 48k?
    48KHz Sample Rate -- Yes, but BM23 must be master and T3.6 slave. This also alters the behavior of certain other Teensey Audio Library objects and makes some unusable.
    24-Bit -- Yes, but not with the Teensey Audio Library. You'll need to implement everything yourself.

  3. #3
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    Thank you for the comprehensive reply! I looked back through the schematic for the BM23 evaluation board, and page 33 shows the I2S connections to the DSP chip. It looks like just DT0, SLK0, and RFS0 are connected.
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  4. #4
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    Looks like you're right. Too bad the I2S write-up in the BM23 datasheet is so poor and uses non-standard signal names.

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