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Thread: i2s slave on teensy 4

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  1. #1
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    i2s slave on teensy 4

    Hi,

    I have a Roland MV8800 sampler. It has an expansion header that provides four "i2s" output streams (8 channels) and an input stream (2 channels). Additionally it has a ttl level midi in and out. I'd like to interface these to a teensy 4.0 and access the midi and audio via usb.

    I've succesfully tested the "i2s" streams using a PCM5102 DAC boards and by looping back an output stream to an input stream.

    The audio streams are 24bit 44.1 khz in a format described as "left justified". It is basically i2s but with the frame sync arriving one bit clock later. There are register bits called frame synce early in I2S_RCR4_FSE and I2S_TCR4_FSE that, according to documentation, can be used for this behaviour if they are cleared.

    The MV8800 is always clock master and offers no configuration in terms of sample rate, format etc.

    For a first pass, I'd like to do stereo in/out loopback at 16bits.

    The pinouts provided in the Audio System Design Tool for the AudioOutputI2Sslave and AudioInputI2Sslave objects are confusing. Are they correct? I would have thought the connections would be MCLK on 23, BCLCK 21, LRCLK 20 and DATA Out on 7 and DATA Out on 8.

    Using the i2s slave objects and the pin's I've mentioned I get noise out that changes depending on what I send to the input.

    I have modified the register settings in output_i2s2.cpp to clear the frame sync early. I've also changed the frame size registers (I2S_TCR4_FRSZ and I2S_RCR4_FRSZ) to 3-1 for the 24bits.

    Any pointers on where I would truncate the 24bits down to 16? Any other pointers would be much appreciated.
    Last edited by widdly; 03-26-2020 at 12:38 AM.

  2. #2
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    Please post a link to the MV8800's I2S documentation.

  3. #3
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    I don't have much documentation. I have a service manual that has a schematic for the device Roland made to connect to the header I'm using. The header and schematic is on pg 59.

    I've figured out the details based on the datasheets of the chips that connect to the i2s lines in the schematic.

    http://www.mediafire.com/file/iu2rs6...VICE_NOTES.pdf

  4. #4
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    When I connected the roland device to the PCM5102 dac I set it to Left Justified mode.

    There is a timing diagram for that on page 14. It would appear that the LRClck is also inverted in that mode. I think there are registers for that on the teensy but if they are not set correctly it would only result in swapped left/right channels.

    Looking at that, I think I would need either a 48fs or 64fs BCLCK.

    http://www.ti.com/lit/ds/symlink/pcm5102.pdf

  5. #5
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    Based on devices I've looked at with I2S (and similar) interfaces, I'm going to guess that the frame size is actually 32 bits and only the upper 24 bits contain valid data. Your best bet is to put a scope on those signals. If I'm right, you'll see that LRCK has a frequency of the sample rate (Fs) -- 44.1 KHz in your case. And, BCLK will be exactly 64 * Fs.

    You should also check the frequency of MCLK. I see references in the schematic to both 384 * Fs and 768 * Fs. The Teensy doesn't need MCLK to receive I2S as a slave. But, some DACs need it. So make sure the DAC you use can accept the MCLK that MV8800 provides.

  6. #6
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    Yep you are correct. I put them on a scope and the FS is at 44.1k, BCLK at 64 * 44.1 and the MCLK is 384 * 44.1

    When I tested with my PCM5102 I didn't need the MCLK

  7. #7
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    Quote Originally Posted by widdly View Post
    When I tested with my PCM5102 I didn't need the MCLK
    That's interesting, according to the Datasheet it does. It's referred to as "System Clock" on Page 11.

  8. #8
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    Read on... page 12 describes a PLL mode that generates it based on LRclk and BCLK.

  9. #9
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    I've got the data out of the teensy on my scope and I can see that disabling frame sync early is not working. The samples are starting a bit after the FS transistion. Looking at the data from the roland, the samples start with the FS transition. I'm going to play around with the TCR and RCR registers.

  10. #10
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    I've got it working for teensy 3.6 I was looking at the slave stuff in output_i2s2.cpp instead of output_i2s.cpp. The frame-sync-early and inverted-frame-sync bits in the SAI registers give the correct left justified handling.

    Not working on teensy 4 with the Teensyduino 1.52 beta. The input to the teensy is fine. The output is formated properly but the actual pcm is a high pitch tone. I've confirmed this using a scope and with an external dac.

    edit. Solved the issue with Teensy 4.

    In the file output_i2s.cpp, I noticed the IMXRT1062 code in AudioOutputI2Sslave::begin() doesn't set the dma.TCS->CSR.
    I added this at line 478...

    dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;

    .. and now the i2s output works.
    Last edited by widdly; 03-27-2020 at 04:23 AM.

  11. #11
    Senior Member+ Frank B's Avatar
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    Could you add a pullrequest at github?
    Thanks!

  12. #12
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    No worries. I pushed some commits for this and to add slave support for i2s oct input.

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