Reading From the SPI FIFO Registers

Guilt · Mar 30, 2020

I've designed the following code for a Teensy 3.6 so that I can familiarize myself with the MCU's hardware:

Code:

#include "Arduino.h"

void dumpTXFIFOSRs() {
  for (uint8_t i = 0; i < 4; i ++) {                                          //for all four fifo registers
    Serial.print(F("txfr")); Serial.print(i,DEC); Serial.print(F("=0b"));     //print some ID
    uint32_t val = KINETISK_SPI0.TXFR[i];                                     //read the register
    for (uint8_t p = 32; p > 0; p--) {                                        //for 32 bit placements,
      if (val<_BV(p)) {                                                       //if the register value doesn't occupy this many bits,
        Serial.print(F("0"));                                                 //print a padding zero
      }
    }
    Serial.println(val,BIN);                                                  //print the register's bit states
  }
}

void setup() {

  
  SIM_SCGC6 |= SIM_SCGC6_SPI0;  //turn on spi0's clock
  SPI0_MCR &= ~SPI_MCR_MDIS;    //turn on the module

  SPI0_PUSHR_SLAVE = 0xffffffff;  //push some data into the FIFO queue
  SPI0_PUSHR_SLAVE = 0x00000001;
  SPI0_PUSHR_SLAVE = 0b11111111111111111111111111111111;


  Serial.begin(115200);

  while(!Serial);
  Serial.println(F("Beginning"));
  dumpTXFIFOSRs();    //figure out what is in the FIFOs
}

void loop() {
}

The MK66FX1M0 Manual says that in SPI slave mode, frame sizes of 32 bits are supported and that SPI0_PUSHR_SLAVE can be filled up with that data. Given this information (and taking into account that the spi module resets to slave mode), I figure that the code above should give me a serial output like the following:

Code:

Beginning
txfr0=0b11111111111111111111111111111111
txfr1=0b00000000000000000000000000000001
txfr2=0b11111111111111111111111111111111
txfr3=0b00000000000000000000000000000000

But it does not! What I get instead is strange!

Code:

Beginning
txfr0=0b11111100111111111111111111111111
txfr1=0b00000000000000000000000000000001
txfr2=0b11111100111111111111111111111111
txfr3=0b00000000000000000000000000000000

It would make some sense to me if that run of zeroes in the middle there had a length of four, because then it would at least match up to the reserved bits in master mode. Is this a hardware glitch or something? Is there another register bit I need to set?

Reading From the SPI FIFO Registers

Guilt

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