Teensy 4.0: possible to receive I2S-Data with 50MHz BCLK ?

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Dirk67

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hello,

is it possible with the Teensy 4.0 to receive I2S-Data up to the speed of 50MHz BCLK ?

(2 channels * 32 bit frame-length * 768kHz sample rate)

Teensy 4.0 has to be I2S-slave / only analysing the data in the frames / no need to process the audio or to put out the (processed) audio again in this case ...

If yes:
can it be done with the already existing arduino libraries for the Teensy 4.0 ?
 
Nope, sorry. That's twice the maximum BCLK frequency.

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Teensy 4.0 does have two I2S ports. So if you could build a small digital logic circuit to divide the clock in half and send each alternating word or bit to each port at 25 MHz, this might be possible.

The first I2S port can also capture up to 4 streams, so this might also be possible using just the main port and putting the bits into 2 of those 4 pins.

I am a bit curious what sort of hardware will generate such an incredibly fast I2S data stream?
 
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