Can a +3.3 voltage be safely applied to the I/O pin of a Teensy 4 while the Teensy 4 power is off?
I can't get a clear answer from the datasheet, which says
4.2.1.3 Power supplies usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, Package information and contact assignments.”
Does this merely mean that it will malfunction if the internal power supply for the pin (NVCC_xxx) is OFF? But what happens when the total power supply is off when malfunction is not possible. Can the I/O circuitry be damaged?
In section 4.3.1 a diagram is shown for the circuitry of the I/O pins. They are driven are driven by complementary pmos and nmos gates. It would seem that with no power both gates would be in a high impedance state and therefore an external 3.3 voltage would be harmless with no current flow.
Help understanding this would be much appreciated.
The background is as follows. I am attaching a uBlox Neo 8m GPS module to the Teensy 4 via Serial 1. I need to keep the GPS module always on, even when the rest of the circuitry is switched off so that a fast hot start is guaranteed. The GPS module will have its own power supply, separate from that of the Teensy circuitry, but will share a common ground.
The GPS module will, by default, continue transmitting data over the serial connection, which means that 3.3 V will be applied to the Rx pin of the Teensy while it is off. When not transmitting data the Tx pin defaults to a high state, 3.3V.
I can't get a clear answer from the datasheet, which says
4.2.1.3 Power supplies usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, Package information and contact assignments.”
Does this merely mean that it will malfunction if the internal power supply for the pin (NVCC_xxx) is OFF? But what happens when the total power supply is off when malfunction is not possible. Can the I/O circuitry be damaged?
In section 4.3.1 a diagram is shown for the circuitry of the I/O pins. They are driven are driven by complementary pmos and nmos gates. It would seem that with no power both gates would be in a high impedance state and therefore an external 3.3 voltage would be harmless with no current flow.
Help understanding this would be much appreciated.
The background is as follows. I am attaching a uBlox Neo 8m GPS module to the Teensy 4 via Serial 1. I need to keep the GPS module always on, even when the rest of the circuitry is switched off so that a fast hot start is guaranteed. The GPS module will have its own power supply, separate from that of the Teensy circuitry, but will share a common ground.
The GPS module will, by default, continue transmitting data over the serial connection, which means that 3.3 V will be applied to the Rx pin of the Teensy while it is off. When not transmitting data the Tx pin defaults to a high state, 3.3V.