Can 3.3 V be safely applied to a Teensy 4 I/O pin while the Teensy 4 power is off?

[PDOS]

Can a +3.3 voltage be safely applied to the I/O pin of a Teensy 4 while the Teensy 4 power is off?

I can't get a clear answer from the datasheet, which says

4.2.1.3 Power supplies usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, Package information and contact assignments.”

Does this merely mean that it will malfunction if the internal power supply for the pin (NVCC_xxx) is OFF? But what happens when the total power supply is off when malfunction is not possible. Can the I/O circuitry be damaged?

In section 4.3.1 a diagram is shown for the circuitry of the I/O pins. They are driven are driven by complementary pmos and nmos gates. It would seem that with no power both gates would be in a high impedance state and therefore an external 3.3 voltage would be harmless with no current flow.

Help understanding this would be much appreciated.

The background is as follows. I am attaching a uBlox Neo 8m GPS module to the Teensy 4 via Serial 1. I need to keep the GPS module always on, even when the rest of the circuitry is switched off so that a fast hot start is guaranteed. The GPS module will have its own power supply, separate from that of the Teensy circuitry, but will share a common ground.

The GPS module will, by default, continue transmitting data over the serial connection, which means that 3.3 V will be applied to the Rx pin of the Teensy while it is off. When not transmitting data the Tx pin defaults to a high state, 3.3V.

 

[AlanK]

Hi,
I've used a Teensy 4.0 connected to an ADC evaluation board that was powered separately, and there was never any problem. There were output pins that were normally HIGH from the eval board, and it was left on while the Teensy was off.

 

[PDOS]

Hi,
I've used a Teensy 4.0 connected to an ADC evaluation board that was powered separately, and there was never any problem. There were output pins that were normally HIGH from the eval board, and it was left on while the Teensy was off.

Thanks for your helpful response.

 

[PaulStoffregen]

Can a +3.3 voltage be safely applied to the I/O pin of a Teensy 4 while the Teensy 4 power is off?

No, you should not do this.

I can't get a clear answer from the datasheet, which says

4.2.1.3 Power supplies usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.

That means you're not supposed to drive the pin while the power is off, either that GPIO section or the whole chip.

In section 4.3.1 a diagram is shown for the circuitry of the I/O pins. They are driven are driven by complementary pmos and nmos gates. It would seem that with no power both gates would be in a high impedance state and therefore an external 3.3 voltage would be harmless with no current flow.

The pins also have diodes to protect against ESD.

Help understanding this would be much appreciated.

Some chips, like the 74LCX logic family, are designed to be high impedance while power is off. But the Teensy 4.0 pins are not.

The GPS module will, by default, continue transmitting data over the serial connection, which means that 3.3 V will be applied to the Rx pin of the Teensy while it is off. When not transmitting data the Tx pin defaults to a high state, 3.3V.

The proper solution would be a buffer chip, like 74LCX125, which is designed to allow its inputs to be driven while it is not powered.

But adding a series resistor between the GPS and Teensy will at least limit the current which can flow into Teensy's pin. That current will flow into the chip at attempt to power up Teensy 4.0. It will almost certainly be enough to keep the RTC & SNVS stuff running, but not enough to let Teensy actually boot up. While not technically following NXP's guidance, current limited to under 1mA is very unlikely to cause harm.

 

[AlanK]

Hi PDOS,

Sorry for giving wrong information. I'm not in a position to check my original setup at the moment - it's in my office and I can't go there,

Good luck

 

[PDOS]

Hi PDOS,

Sorry for giving wrong information. I'm not in a position to check my original setup at the moment - it's in my office and I can't go there,

Good luck

No harm done. We all do the best we can.

it's in my office and I can't go there,

We are all in the same boat, though happily not a cruise ship.

 

[PDOS]

No, you should not do this.

The proper solution would be a buffer chip, like 74LCX125, which is designed to allow its inputs to be driven while it is not powered.

Paul, thanks for your informative reply.
Happily I have some IO bus buffer chips (74AHC126N) on hand. From the datasheet:

The 74AHC126 provides provides four independent buffer gates with
3-state outputs. Each buffer has a separate enable pin that when
driven with a low logic level places the corresponding output in the
high-impedance state. The device is designed for operation with a
power supply range of 2.0V to 5.5V. The inputs are tolerant to 5.5V
allowing this device to be used in a mixed voltage environment.

I am thinking of tying the buffer output enable pin to the Teensy's power supply so that when it is switched off the output enable goes low, placing the buffer output in a high impedance state.

 

[PaulStoffregen]

Not all buffer chips are created equal. 5V tolerance and allowing the pin to be driven higher than the power rail is a good sign, but does not necessarily mean the chip's inputs can be driven while power is off.

I recommend looking for a chip which specifically says it is high impedance when power is off. I know the 74LCX buffer chips have that as a specific feature they advertise.