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Thread: Teensy 4.1 Beta Test

  1. #1
    Senior Member PaulStoffregen's Avatar
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    Teensy 4.1 Beta Test

    Edit: Teensy 4.1 was released on May 11, 2020. The beta test is finished. You can buy Teensy 4.1 now.

    https://www.pjrc.com/store/teensy41.html



    We will soon begin a public beta test for Teensy 4.1.

    At this time, PJRC would like to offer free Teensy 4.1 boards to the following people:

    AdmiralCrunch, adrianfreed, Arctic_Eddie, bicycleguy, Bill Greiman, Blackaddr, blackketter, bmillier, bossredman, brendanmatkin, brtaylor, chipaudette, Chris O., christoph, CorBee, crees, danixdj, DaQue, DD4WH, defragster, DerekR, Don Kelly, Donziboy2, duff, easone, edrummer, Elmue, el_supremo, ETMoody3, flashburn, Frank B, Gadget999, Gerrit, gfvalvo, Gibbedy, GremlinWrangler, hubbe, HWGuy, ikravets, JBeale, jbliesener, jcarruthers, Jean-Marc, jeffmhopkins, jimmayhugh, john-mike, jonr, Jp3141, jwatte, Koromix, kriegsman, KrisKasprzak, KurtE, LenSamuelson, loglow, luni, manitou, markonian, Markus_L811, MichaelMeissner, MickMad, mjs513, mlu, mortonkopf, mxxx, Nantonos, neurofun, nlecaude, Nominal Animal, nox771, oddson, Paul Hesketh, PaulS, Pedvide, Pensive, pictographer, Pointy, potatotron, Po Ting, prickle, Projectitis, rcarr, RichardFerraro, shawn, sumotoy, tannewt, Teenfor3, TelephoneBill, tenkai, Theremingenieur, tni, tonton81, tubelab.com, turtle9er, urbanspaceman, visual_micro, vjmuzik, wangnick, Ward, Wayne, wcalvert, widdly, WMXZ, Wozzy, wwatson, XFer, xxxajk, yeahtuna

    We've already sent early boards to 5 people on this list. Another 24 boards pre-production boards are available now, but there is a minor catch. These 24 boards have a mistake where one of the 3.3V pins and two GND pins aren't connected, due to an error in how the PCB panelization was done for this small pre-production batch. Otherwise, these 24 boards do work fine, you just can't use those 3 power pins.

    Everyone on this list who does not receive a pre-production board will be offered a free Teensy 4.1 from the first production batch (which will have all power pins correct). If you're busy right now, or you'd just prefer to wait for the production batch, there is no need to do anything right now. We expect to release Teensy 4.1 sometime in May, so the wait will not be long...

    If you'd like a pre-production Teensy 4.1 now, please email me directly (paul at pjrc dot com) with the magic words "I have time to beta test 4.1 and give feedback on the forum". Please mention your forum user name, and if sending from a different address than you've used for this forum, you must mention the email address registered to your forum account. There is no charge for these betas. PJRC will pay for shipping. If you're outside the USA and the carrier charges international tariff/vat/fees when the package arrives, you'll need to cover that cost. We can't pre-pay it from here.

    EDIT: Photos are ok now that Teensy 4.1 has been released.

    Maybe you're curious about the specs? Teensy 4.1 uses the same 600 MHz IMXRT1062 microcontroller as Teensy 4.0. The PCB is the larger 48-pin form factor (same as Teensy 3.5 & 3.6), which provides more I/O pins and easier access the SD card and USB Host. Teensy 4.1 has an 8 MB flash chip, an Ethernet PHY, and places on the bottom side to solder QSPI memory chips.

  2. #2
    Senior Member PaulStoffregen's Avatar
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    placeholder post: latest software

  3. #3
    Senior Member PaulStoffregen's Avatar
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    Pinouts & technical info:

    Click image for larger version. 

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    Adapter board and info for connecting Ethernet: (click "Description" button for parts list)
    https://oshpark.com/shared_projects/5epewE3O

  4. #4
    Senior Member PaulStoffregen's Avatar
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    placeholder post: known issues

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    Fantastic! Really looking forward to this. Any chance you'll be releasing the exact pin assignments early, or does that fall under the no photos policy?

  6. #6
    Senior Member PaulStoffregen's Avatar
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    Yes, I will post pinout info soon to msg #3. I had meant to create it this weekend, but we ended up spending all weekend putting together orders to restock distributors, so the supply of Teensy doesn't run out. With Oregon's covid-19 shelter-in-place, our 2 people who normally package Teensy can't work. PJRC is currently down to just Robin & me!

    If you want the info pinout now, in a not-so-pretty format, you can get it 2 ways.

    The main pinout (42 I/O on outside edges) is exactly the same as this message from December.

    The pins are also defined in this core library header file. Pins 42-47 map to the SD card, the same as the bottom-side SD pins on Teensy 4.0. Pins 48-54 map to the bottom-side pads for adding QSPI chips.

  7. #7
    Senior Member+ KurtE's Avatar
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    For what it is worth, I have updated my Excel document for the pinouts up on my github project: https://github.com/KurtE/TeensyDocum...y4%20Pins.xlsx
    Which is an excel document which has a couple of pages on the T4.1 pins.

    Code:
    Pin	Name	GPIO	Serial	I2C	SPI	PWM	CAN	Audio	XBAR	FlexIO	Analog	SD
     0	AD_B0_03	1.3	Serial1(6) RX		SPI1(3) CS0	PWM1_X1	2_RX		IO-17			
     1	AD_B0_02	1.2	Serial1(6) TX		SPI1(3) MISO	PWM1_X0	2_TX		IO-16			
     2	EMC_04	4.4				PWM4_A2		2:TX_DATA	IO-06	1:4		
     3	EMC_05	4.5				PWM4_B2		2:TX_SYNC	IO-07	1:5		
     4	EMC_06	4.6				PWM2_A0		2:TX_BCLK	IO-08	1:6		
    5	EMC_08	4.8				PWM2_A1		2:RX_DATA	IO-17	1:8		
    6	B0_10	2.10				PWM2_A2, QT4_1		1:TX3_RX1		2:10		
    7	B1_01	2.17	Serial2(4) RX			PWM1_B3		1:TX_DATA	IO-15	2:17, 3:17		
    8	B1_00	2.16	Serial2(4) TX			PWM1_A3		1:RX_DATA	IO-14	2:16, 3:16		
     9	B0_11	2.11				PWM2_B,QT4_2		1:TX2_RX2		2:11		
    10	B0_00	2.0			SPI(4) CS0	QT1_0		MQS_RIGHT		2:0     		
    11	B0_02	2.2			SPI(4) MOSI	QT1_2	1_TX			2:2		
    12	B0_01	2.1			SPI(4) MISO	QT1_1		MQS_LEFT		2:1     		
    13	B0_03	2.3			SPI(4) SCK	QT2_0	1_RX			2:3		
    14/A0	AD_B1_02	1.18	Serial3(2) TX			QT3_2		SPDIF_OUT		3:2	A1:7, A2:7	
    15/A1	AD_B1_03	1.19	Serial3(2) RX			QT3_3		SPDIF_IN		3:3	A1:8, A2:8	
    16/A2	AD_B1_07	1.23	Serial4(3) RX	Wire1(3) SCL				SPDIF_EXTCLK		3:7	A1:12, A2:12	USDHC2_DATA3
    17/A3	AD_B1_06	1.22	Serial4(3) TX	Wire1(3) SDA				SPDIF_LOCK		3:6	A1:11, A2:11	USDHC2_DATA2
    18/A4	AD_B1_01	1.17	Serial3(2) RTS	Wire(1) SDA		QT3_1				3:1	A1:6, A2:6	
    19/A5	AD_B1_00	1.16	Serial3(2) CTS	Wire(1) SCL		QT3_0				3:0	A1:5, A2:5	
    20/A6	AD_B1_10	1.26	Serial5(8) TX					1:RX_SYNC		3:10	A1:15, A2:15	
    21/A7	AD_B1_11	1.27	Serial5(8) RX					1:RX_BCLK		3:11	A1:0, A2:0	
    22/A8	AD_B1_08	1.24				PWM4_A0	1_TX			3:8	A1:13, A2:13	USDHC2_CMD
    23/A9	AD_B1_09	1.25				PWM4_A1	1_RX	1:MCLK		3:9	A1:14, A2:14	USDHC2_CLK
    ---	----	----	------	---	---	---	---	----	----	-----	------	
    24/A10	AD_B0_12	1.12	Serial6(1) TX	Wire2(4) SCL		PWM1_X2					A1:1  	
    25/A11	AD_B0_13	1.13	Serial6(1) RX	Wire2(4) SDA		PWM1_X3	GPT1_CLK				A1:2	
    26/A12	AD_B1_14	1.30			SPI1(3) MOSI			1:TX_BCLK		3:14	A2:3  	
    27/A13	AD_B1_15	1.31			SPI1(3) SCK			1:TX_SYNC		3:15	A2:4  	
    28	EMC_32	3.18	Serial7(7) RX			PWM3_B1						
    29	EMC_31	4.31	Serial7(7) TX		SPI2(1) CS1	PWM3_A1						
    30	EMC_37	3.23				GPT1_3 	3_RX	3:MCLK	IO-23			
    31	EMC_36	3.22				GPT1_2	3_TX	3:TX_DATA	IO-22			
    32	B0_12	2.12						1:TX1_RX3	IO-10	2:12		
    33	EMC_07	4.7				PWM2_B0		2:MCLK	IO-09	1:7		
    Warning Guessing on actual pin number ordering Here												
    New Top Pins(Pin numbers from Forum posting)												
    34	B1_13    	2.29	Serial8(5) RX							2:29,3:29		
    35	B1_12    	2.28	Serial8(5) TX							2:28,3:28		
    36	B1_02    	2.18			SPI(4) CS2 	PWM2_A3		1:TX_BCLK 	IO-16	2:18,3:18		
    37	B1_03    	2.19			SPI(4) CS1 	PWM2_B3		1:TX_SYNC 	IO-17	2:19,3:19		
    38/A14	AD_B1_12 	1.28			SPI1(3) CS0 			1:rx_data 		3:12	A2:1	
    39/A5	AD_B1_13 	1.29			SPI1(3) MISO			1:tx_data 		3:13	A2:2	
    40/A16	AD_B1_04 	1.2								3:4	A1:9,A2:9	USDHC2_DATA0
    41/A17	AD_B1_05 	1.21				GPT2_1				3:5	A1:10,A2:10	USDHC2_DATA1
    SD Pins - Cable connector(T4 34-39)												
    42	SD_B0_03	2.15	Serial5(8) RTS		SPI2(1) MISO	PWM1_B1			IO-07			DATA1
    43	SD_B0_02	3.14	Serial5(8) CTS		SPI2(1) MOSI	PWM1_A1			IO-06			DATA0
    44	SD_B0_01	3.13		Wire1(3) SDA	SPI2(1) CS0	PWM1_B0			IO-05			CLK
    45	SD_B0_00	3.12		Wire1(3) SCL	SPI2(1) SCK	PWM1_A0			IO-04			CMD
    46	SD_B0_05	3.17	Serial5(8) RX		FLEXSPI B_DQS	PWM1_B2			IO-09			DATA3
    47	SD_B0_04	3.16	Serial5(8) TX		FLEXSPI B_SSO_B	PWM1_A2			IO-08			DATA2
    Bottom Memory Connectors												
    48	EMC_24	4:24	Serial8(5) RX 		FLEXSPI2_A_SS0_B	PWM1_B0						
    49	EMC_27	4:27	Serial8(5) RTS		FLEXSPI2_A_DATA01, SPI2(1) SCK  	PWM1_A2				1:13		
    50	EMC_28	4:28	Serial8(5) CTS		FLEXSPI2_A_DATA02, SPI2(1) MOSI	PWM1_B2				1:14		
    51	EMC_22	4:22		Wire1(3) SCL	FLEXSPI2_A_SS1_B	PWM3_B3, QT2_3						
    52	EMC_26	4:26	Serial1(6) RX 		FLEXSPI2_A_DATA00	PWM1_B1				1:12		
    53	EMC_25	4:25	Serial1(6) TX 		FLEXSPI2_A_SCLK	PWM1_A1						
    54	EMC_29	4:29	Serial1(6) RTS		FLEXSPI2_A_DATA03, SPI2(1) MISO	PWM3_A0				1:15
    The other page is sort of like the extended card view. Right now for a place holder it shows an image of the T4 mounted in the FRDM4236, which gave it a T3.6 form factor for the two outside rows of pins... So used it to give a sort of idea on where the outside pins are...

  8. #8
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    Thank you KurtE for the pinout spreadsheet.

    How comes there is MISO1 on D1 and another MISO1 on D39 ?

  9. #9
    Senior Member+ KurtE's Avatar
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    Like most Teensy boards, some functionality can be on two different pins, only one is used at a time).

    In this example pin 1 is the default for MISO pin for SPI1 (i.e. the same as for T4).
    However you can use pin 39 on T4.1 instead by doing: SPI1.setMISO(39);

    The Card version shows the text colors different for the NON default pins, in the case of T4.1(and T4) there are not many of these.


    Also notes:
    The SPI library was updated as part of the current beta releases to be able to use this.
    Also updated as SPI1 also has an alternate CS pin (This is also the CS0 on SPI1 like pin 0 is). Note this only matters on those few libraries (like a few of our display drivers), that use the hardware CS and likewise for those who do slave mode SPI.

    The SPI object also has two new CS pins, These are actually CS1 and CS2 on the SPI object. There are not duplicates of the CS0 but are distinct CSs... Some of the display libraries were updated to also work with these pins. Note: Slave mode CS for SPI is only supported on the CS0 pin...

    @Paul - Are you going to release a new beta release with the T4.1 defined in boards.txt? I am not sure if all of the Pull Requests for some of this have been incorporated yet or not.

  10. #10
    Senior Member+ MichaelMeissner's Avatar
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    Quote Originally Posted by KurtE View Post
    Like most Teensy boards, some functionality can be on two different pins, only one is used at a time).

    In this example pin 1 is the default for MISO pin for SPI1 (i.e. the same as for T4).
    However you can use pin 39 on T4.1 instead by doing: SPI1.setMISO(39);
    In particular, on the Teensy 4.0, if you used the second SPI bus, you could not use the main serial terminal (Serial1). Now, you can use the 2nd SPI bus and use Serial1 at the same time.

    Quote Originally Posted by KurtE View Post
    The Card version shows the text colors different for the NON default pins, in the case of T4.1(and T4) there are not many of these.

    Also notes:
    The SPI library was updated as part of the current beta releases to be able to use this.
    Also updated as SPI1 also has an alternate CS pin (This is also the CS0 on SPI1 like pin 0 is). Note this only matters on those few libraries (like a few of our display drivers), that use the hardware CS and likewise for those who do slave mode SPI.

    The SPI object also has two new CS pins, These are actually CS1 and CS2 on the SPI object. There are not duplicates of the CS0 but are distinct CSs... Some of the display libraries were updated to also work with these pins. Note: Slave mode CS for SPI is only supported on the CS0 pin...

    @Paul - Are you going to release a new beta release with the T4.1 defined in boards.txt? I am not sure if all of the Pull Requests for some of this have been incorporated yet or not.
    I assume the usual suspects for display libraries have been updated? I.e. with 3 h/w CS pins, we should be able to see speed ups in the displays that had special support for the Teensy 3.x (i.e. ST7735, etc.).

  11. #11
    Senior Member PaulStoffregen's Avatar
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    Quote Originally Posted by KurtE View Post
    Are you going to release a new beta release with the T4.1 defined in boards.txt? I am not sure if all of the Pull Requests for some of this have been incorporated yet or not.
    Yes. My tentative plan is to start shipping the beta boards tomorrow (Tuesday) and publish a new 1.52 beta with Teensy 4.1 in the Tools>Boards menu on Wednesday.

    So far only a few of the 24 pre-production boards have been claimed. If anyone on the list is reading this and holding back to let others have a chance, don't be shy. If we still have unclaimed boards by Thursday, I'll start sending email updates, as many people on this list probably aren't watching the forum on the daily basis. Anyone who is gets to choose first.


    Quote Originally Posted by MichaelMeissner View Post
    with 3 h/w CS pins, we should be able to see speed ups in the displays that had special support for the Teensy 3.x (i.e. ST7735, etc.).
    Sadly, the SPI hardware in Teensy 4.x doesn't provide control of more than 1 CS pin at a time, like we have on Teensy 3.x. So some of those speedup tricks won't be possible.

  12. #12
    Senior Member+ KurtE's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    Yes. My tentative plan is to start shipping the beta boards tomorrow (Tuesday) and publish a new 1.52 beta with Teensy 4.1 in the Tools>Boards menu on Wednesday.
    Sounds great!

    Quote Originally Posted by PaulStoffregen View Post
    Sadly, the SPI hardware in Teensy 4.x doesn't provide control of more than 1 CS pin at a time, like we have on Teensy 3.x. So some of those speedup tricks won't be possible.
    Actually what I found working with T3.x drivers on T3.5/6 beta where SPI1 only had one CS pin, I found with the ili9341_t3n, you did not lose a whole lot of speed with just one hardware CS pin as long as it was used for the DC pin. So in most of the libraries I made have the CS pin on hardware CS as optional... The main reason was in most cases of setting/clearing the CS pin is more or less done when you make calls to beginTransaction/endTransaction and in most all of these cases even with hardware CS pin we still did a wait until transmit complete at same time anyway...

    With T4.x - Still have some of the same things. The driver do try to use a hardware CS pin if you specify it for the DC pin. This does allow the queue to continue doing stuff.
    Note: The FIFO queues and instructions are different.
    With T3.x PUSHR register you can specify which of the CS pins to set... (and if to hold after)... So we could encode both cS and DC on this.

    With T4.x the TDR register only pushes data onto the FIFO (can be up to 32 bits of data). You can change which (by index) of the CS pins to set/hold with data set to the TCR register which also pushes onto the FIFO queue.

    Hopefully this is clear as mud
    Last edited by defragster; 04-20-2020 at 11:10 PM. Reason: fix quote]

  13. #13
    Senior Member+ manitou's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    Yes. My tentative plan is to start shipping the beta boards tomorrow (Tuesday) and publish a new 1.52 beta with Teensy 4.1 in the Tools>Boards menu on Wednesday.
    Re:1.52 beta
    The current Audio lib on github has a compile error. there is a pull-request which fixes it, me thinks.

  14. #14
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    Originally Posted by PaulStoffregen
    Anyone who is gets to choose first.
    Woohoo I guess I'm a lucky guy.

  15. #15
    Will the 4.1 have access to usb D+/- as pads like the 3.6?

  16. #16
    Senior Member duff's Avatar
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    Oh cool, I just pushed an update to Snooze for T4.0 support. I guess I'll have to add T4.1 support now too I'm considering T4 support beta now but it seems to work for me, haven't looked at any current measurements yet will do that in next few days.

  17. #17
    Senior Member+ KurtE's Avatar
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    @neroroxxx - If you are asking if it will have the D+/D- pins that on T3.x you could replace the main USB connector, I am pretty sure the answer is NO. Again I believe the issue has to do with this USB like the T4, can go a whole lot faster than the T3.x USB connections and needs to be as short as possible.

    If you are asking if it has a USB Host connector pins like the T3.6, than yes

  18. #18
    yes i was asking about usb not the usb host, that sucks i really like being able to make breakout boards with USB B jacks instead of micro USB but i get it

  19. #19
    Senior Member PaulStoffregen's Avatar
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    I've added a first rough draft for the pinout card to msg #3.


    Quote Originally Posted by neroroxxx View Post
    yes i was asking about usb not the usb host
    I did bring the 2 USB device signals to small test pads on the bottom side on the final PCB rev (but not on the earliest prototypes). They're not nearly as large as the pads on Teensy 3.6, due to concerns about 480 Mbit/sec signals.

  20. #20
    Hopefully a well placed set of pogo pins would work on those, ill be getting a 4.1 as soon as they are released!

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    Are there plans for a TCP/IP stack for the Teensy 4.1 ?

  22. #22
    Senior Member+ defragster's Avatar
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    Quote Originally Posted by PaulStoffregen View Post
    I've added a first rough draft for the pinout card to msg #3.
    ...
    That shows red-lined the …"boards have a mistake where one of the 3.3V pins and two GND pins aren't connected" … versus " production batch (which will have all power pins correct)"

    Interior items not shown in Msg #3:
    > T_4.0 End pins shifted to the same location as the row on the T_3.6 with T_4.0's On/Off not reset
    > USB Host through holes with the same location as the T_3.6 with T_4.0 bottom pins migrated
    > SD card end socket like T_3.6 with T_4.0 bottom pins migrated
    > Ethernet PHY - onboard ready with smaller 6 pin header to be soldered and cable interfaced to a MAG unit

    All other T_4.0 bottom pads/pins were moved to edges of the elongated T_4.1, and new pins filled in.
    *noted in p#19 that small Device USB pads for D+/D- were added where they existed on T_3.x's.
    Bottom maintains the cut trace for VIN<>VUSB and the VUSB through hole.
    Layout added on the bottom side to solder 2 QSPI memory chips. One larger/FLASH like Audio board, the other smaller pitch RAM fits the common 8MB PSRAM.
    Quote Originally Posted by PaulStoffregen View Post
    The RAM chips I've tested are IPS6404L-SQ-SPN and ESP-PSRAM64H. Both seem to work fine, and very likely are exactly the same silicon inside.
    The flash chip tested so far is W25Q128JVSIQ.
    Quote Originally Posted by Logs View Post
    Are there plans for a TCP/IP stack for the Teensy 4.1 ?
    There has been some testable work with the onboard ethernet. It is fast and functional - time will tell when it evolves as needed.
    Last edited by defragster; 04-21-2020 at 10:15 PM. Reason: added tested chip post

  23. #23
    Senior Member+ manitou's Avatar
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    Quote Originally Posted by Logs View Post
    Are there plans for a TCP/IP stack for the Teensy 4.1 ?
    The T4.1 Ethernet is very similar to T3.5/3.6 Ethernet. There is no custom T4.1 ethernet lib yet, but the lwIP lib works like it did with T3.5/3.6 beta testing

    See post #108 for T4.1 Ethernet summary.

    SdFat-beta was updated to support T4.1 on 4/24/20

    https://github.com/PaulStoffregen/teensy41_ethernet
    Last edited by manitou; 04-28-2020 at 02:17 PM.

  24. #24
    Senior Member PaulStoffregen's Avatar
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    Ten of the 24 pre-production boards have been claimed so far. Those 10 will go into the mail today.

    In case it wasn't clear, we're only sending the Teensy 4.1 beta tests to the people specifically listed on msg #1.

    If you're on the list and want to beta test, just email me and we'll get you one of the remaining 14 boards.

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    Hi Paul,

    Great job again!
    I think a lot of people were waiting for a T3.6 form factor again.
    I am very impatient to experiment with the QSPI memory chip on that device...
    Any clue of the device that could be soldered directly underneath? Something we could pre-order?

    Thanks for all the work you and your team put in this project, looking at the circumstances.

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