PWM Interrupt on Teensy 4.0

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Edmund

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I wanted to trigger an interrupt each time the PWM is reloaded.

Therefore, I added the interrupt routine

void TIMER() {
ie++;
asm("dsb");
}

and the following lines at the end of setup:

attachInterruptVector(IRQ_FLEXPWM2_0, TIMER);
NVIC_ENABLE_IRQ(IRQ_FLEXPWM2_0);
FLEXPWM2_SM0INTEN |= FLEXPWM_SMINTEN_RIE ; // Reload Interrupt Enable

The program stops at this point (no further output on serial, PWM still running).

Any idea what is wrong or missing?

Best regards
 
Most peripheral interrupts in this chip have a flag in the peripheral which you must clear before your interrupt returns. If you don't clear that flag, it just keeps infinitely interrupting and your program never gets to run.
 
Thanks Paul,

FLEXPWM2_SM0STS |= FLEXPWM_SMSTS_RF; // Clear Reload

was missing in the IE-Routine.
Clearing is done by writing a 1 to the bit, a little strange but explained on page 3100 in the Processor Reference Manual.
 
That's how the interrupt bits work in pretty much every peripheral in this chip. Writing 1 clears the interrupt flag, writing 0 leaves it unchanged.

The idea is you can read a register with lots of those flags, then write the same value you just read back to it to clear the flags which were active at the time of your read. Because writing a zero has no effect, if another hardware event occurs during the brief moment to set one of the other bits, your write with a zero in that bit won't clobber that freshly set flag, so you don't "lose" that event. Some peripherals even have a sort of double buffering, to remember you read a 1 bit, so if another event occurs to set that bit again after your read, your next write with a 1 bit that would have cleared that flag doesn't actually clear it, so you get another interrupt for that next event which happened while your code was servicing the previous event.

Many modern chips are using this write-1-to-clear approach for interrupt flags. It may seem strange at first to write 1 to get zero, but it's actually a pretty awesome feature that lets you write simple & efficient code without risking race conditions that might miss hardware events.
 
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