31.6.2.3 Noise-induced errors
System noise that occurs during the sample or conversion process can affect the accuracy of the conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are met:
• There is a 0.1 μF low-ESR capacitor from VREFH to VREFL.
[Already taken care of on the Teensy 3.2 board.]
• There is a 0.1 μF low-ESR capacitor from VDDA to VSSA.
[Teensy 3.2 is using 0.1μF and 470Ω in series between these pins.]
• If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from VDDA to VSSA.
[Teensy 3.2 is using 2.2μF here.]
• VSSA, and VREFL, if connected, is connected to VSS at a quiet point in the ground plane.
[Taken care of on the Teensy 3.2 board.]
• Operate the MCU in Wait or Normal Stop mode before initiating (hardware-triggered conversions) or immediately after initiating (hardware- or software-triggered conversions) the ADC conversion.
• For software triggered conversions, immediately follow the write to SC1 with a Wait instruction or Stop instruction.
• For Normal Stop mode operation, select ADACK as the clock source. Operation in Normal Stop reduces VDD noise but increases effective conversion time due to stop recovery.
• There is no I/O switching, input or output, on the MCU during the conversion.
[I don't know what any of those four points mean, exactly. I wonder - are any of them used in Pedvide's ADC library? Or is that library only doing the ADCK and averaging stuff below?]
There are some situations where external system activity causes radiated or conducted noise emissions or excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in Wait or Normal Stop mode, or I/O activity cannot be halted, the following actions may reduce the effect of noise on the accuracy:
• Place a 0.01 μF capacitor (CAS) on the selected input channel to VREFL or VSSA. This improves noise issues, but affects the sample rate based on the external analog source resistance.
[As you mentioned.]
• Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1 LSB, one-time error.
[Easy enough in the ADC library, and it helps.]
• Reduce the effect of synchronous noise by operating off the asynchronous clock, that is, ADACK, and averaging. Noise that is synchronous to ADCK cannot be averaged out.
[I assume Pedvide's ADC library is doing this, since it mentions ADCK speed.]